The disclosure of transient execution attacks, such as Meltdown and Spectre, has once again highlighted the threat of cache side-channel configurations. It has now been demonstrated that the cache hierarchy of modern processors functions as a micro-architectural medium where the transient execution may leak private data, in addition to also serving as an attack surface that adversaries can use to directly spy on victim programs. As a response to tamper the effectiveness of cache side-channel configurations, hardware manufacturers, and most notably AMD, have now opted to reduce the processor’s cycle counter resolution to prevent adversaries from mounting side-channels in the higher levels of the cache hierarchy, specially in the L1D cache. This partially works because classic cache side-channel techniques, namely Prime+Probe or Flush+Reload, heavily rely on the processor’s cycle counter to detect changes in the cache state, which is normally done by tracking cache hits and misses. Yet, we present The Race-Timing Prototype to prove that devoted adversaries no longer rely on the processor’s cycle counter resolution to effectively distinguish cache hits from misses, and that a cache side-channel can still be configured by only utilizing controlled memory race conditions. In view that our implementation is hardware agnostic and does not rely on any proprietary instruction set extension, we demonstrate that our prototype works on processors from both Intel and AMD. Additionally, with propose a new semantic of Out-of-Order Detachment that further allows our Race-Timing measurements to closely match the accuracy of hardware Performance Monitoring Counters to distinguish fast L1D and L2 cache accesses in Intel processors. Ultimately, this work demonstrates that an adversary can exploit a cache side-channel with high-precision timing, and without utilizing cycle counters at all.

Handheld devices, such as smartphones and tablets, currently dominate the semiconductor market. The memory access patterns of CPU and IP cores are dramatically different in a handheld device, making the main memory a critical bottleneck of the entire system. As a result, non-volatile memories, such as spin transfer torque magnetoresistive random-access memory (STT-MRAM), are emerging as a replacement for the existing DRAM-based main memory, achieving a wide variety of advantages. However, replacing DRAM with STT-MRAM also results in new design challenges including read disturbance. A simple read-and-restore scheme preserves data integrity under read disturbance, but incurs significant performance and energy overheads. Consequently, by utilizing unique characteristics of mobile applications, we propose FlowPaP, a flow pattern prediction scheme to dynamically predict the write-to-last-read distances for data frames running on a handheld device. FlowPaP identifies and removes unnecessary memory restores originally required for preventing read disturbance, significantly improving energy efficiency and performance for STT-MRAM-based handheld devices. In addition, we propose a flow-based data retention time reduction scheme named FlowReR to further lower energy consumption of STT-MRAM at the expense of reducing its data retention time. FlowReR imposes a second step that marginally trades off the already improved energy efficiency for performance improvements. Experimental results show that, compared to the original read-and-restore scheme, the application of FlowPaP and FlowReR together can simultaneously improve energy efficiency by 34% and performance by 17% for a set of commonly used Android applications.

Mobile devices, especially smartphones are increasingly gaining ground in several domains, particularly healthcare, tele-monitoring, and education to perform Resource-intensive Mobile Applications (RiMA). However, constrained resources, especially CPU and battery hinder their successful adoption. Mobile Cloud Computing (MCC) aims to augment computational capabilities of resource-constraint mobile devices and conserve their native resources by remotely performing intensive tasks. In typical MCC solutions, intensive tasks are offloaded to distant VM-based cloud data centers or cloudlets whose exploitation originates long WAN latency and/or virtualization overhead degrading RiMA execution efficiency. In this paper, a lightweight Resource-oriented MCC (RMCC) architecture is proposed that exploits resources of plethora of Adjacent Service-based Mobile Cloudlets (ASMobiC) as fine-grained mobile service providers. In RMCC, ASMobiCs host prefabricated Restful services to be asynchronously called by mobile service consumers at runtime. RMCC is a Restful cross-platform architecture functional on major mobile OSs (e.g., Android and iOS) and realizes utilization of the computing resources of off-the-shelve outdated or damaged-yet-functioning mobile devices towards green MCC. Results of benchmarking advocate significant mean time- and energy-saving of 87% and 71.45%, respectively when intensive tasks are executed in ASMobiCs.

Hashing techniques have been widely adopted for general IP address lookup and specific network intrusion detection. In most current commonly used XOR-hashing algorithms, each of the hash key bits is usually explicitly XORed only at most once in the hash process, which may limit the amount of potential randomness that can be introduced by the hashing process. This paper further looks into various ways in duplicating and re-using key bits to maximize randomness needed in the hashing process so as to enhance the overall performance further.

Hash results delivered by traditional hashing algorithms usually are far from optimal when the database presented is not uniformly distributed. This paper proposes a unique hashing algorithm to tackle such a non-uniformly distributed database prevalent in computer network applications. The original database is first pre-processed to extract information that would facilitate the design of an ad-hoc hashing algorithm

Hashing algorithms have been widely adopted to provide a fast address look-up process which involves a search through a large database to find a record associated with a given key. Modern examples include address-lookup in network routers for a forwarding outgoing link, rule-matching in intrusion detection systems comparing incoming packets with a large database, etc. Hashing algorithms involve transforming a key inside each target data to a hash value hoping that the hashing would render the database a uniform distribution with respect to this new hash value. When the database are already key-wise uniformly distributed, any regular hashing algorithm would easily lead to perfectly uniform distribution after the hashing. On the other hand, if records in the database are instead not uniformly distributed, then different hashing functions would lead to different performance. This paper addresses the case when such distribution follows a natural negative linear distribution, which is found to approximate distributions in many various applications. For this distribution, we derive a general formula for calculating the distribution variance produced by any given non-overlapped bit-grouping XOR hashing function. Such a distribution variance from the hashing directly translates to performance variations in searching. In this paper, the best XOR hashing function is determined for any given key size and any given hashing target size.

The mesh is a widely used architecture in parallel computing systems. Research on efficient allocation of processors to incoming tasks on a mesh architecture is very important in achieving the desired high performance. The processor allocation strategy proposed in this paper is based on a well-known boundary search approach by considering allocation time similarity as another primary allocation decision-making factor. In this proposed technique, an additional novel heuristic is employed to consider allocating tasks with similar allocation times with submeshes adjacent to each other, whenever feasible. The external fragmentation problem is expected to be alleviated, which leads to improvement in, better utilization and shorter task waiting time. Our simulation results demonstrate a substantial improvement.

A new approach, look-ahead traffic distribution, is proposed in this paper to improve the performance of adaptive routing algorithms in wormhole routed networks. In most adaptive routing algorithms, a packet changes its forwarding direction only if its requesting channel is not available, i.e., the routing decision is based only on the traffic information (buffer availability) in adjacent nodes. The performance of these adaptive routing algorithms usually is far from optimal due to such a crude routing decision-making process without taking into consideration traffic information in non-adjacent nodes which a packet potentially is to be forwarded to at a later time. By adding minimal hardware to the router, the proposed approach allows neighboring routers to exchange integrated traffic information and each router to re-integrate information gathered before further propagation. It is intended to use a small amount of such integrated information to give each router a sketch of semi-global traffic information and degree of congestion in an extended local area. Such information is then used for a more intelligent routing decision-making process in each router. Experimental results show that the communication latency and the saturation point have been significantly improved by applying such an add-on feature to existing adaptive algorithms.

An efficient implementation of a consistent labeling technique can lead to a fast solution in solving all kinds of tree search problems by reducing the search space from a potentially exponential size to a much smaller size. In this paper a scalable parallel algorithm is presented in achieving labeling consistency. This algorithm is optimal in execution time as well as in processor-time product. It is suitable for implementation on most distributed memory multiprocessor system.

Discrete relaxation technique has been widely used in pattern recognition, artificial intelligence and computer vision. For the consistent labeling problem for labeling n objects with m labels, a parallel implementation based on a new sequential algorithm is shown. This non-partitioned parallel implementation runs in O(nm) time using nm PE's. Two partitioned implementations are then proposed. In the first implementation, O(n/sup 2/m/sup 2//P) time performance is achieved by using P PE's connected to a common bus, where Por=P/sup 2/.>

Three parallel implementations based on three alternate sequential approaches are presented. The first design is a systolic array based on the known sequential method. An execution time of O(n/sup 2/m/sup 2/) is achieved with nm processing elements (PEs), with each PE composed of simple logic elements. The second design employs broadcast bus feature to speed up the execution of an alternate sequential method. Linear speedup is achieved by using nm processing elements. The sequential method has an execution time of O(n/sup 2/m/sup 2/) and the proposed parallel design runs in O(nm) time. The third design is a modified approach which is well suited for implementation on general-purpose machines. These designs achieve superior performance compared with the existing designs in terms of their simplicity, execution time, and domain of applications. Using the proposed designs, an efficient parallel implementation of stereo matching based on linear segments as primitives is derived.>

Implementations of neural networks on programmable massively parallel computers are addressed. The methods are based on a graph theoretic approach and are applicable to a large class of networks in which the computations can be described by means of matrix and vector operations. A detailed characterization of the target machine is provided. Two mappings are presented. The first is designed for a processor array consisting of a very large number of small processing units. The neurons and the nonzero synaptic weights are assigned to the processors in a predetermined order, one per processor. The data transfers between processors containing neurons and weights are implemented using a novel routing algorithm. The second mapping is designed for the data array of size N*N and a smaller processor array of size P*P, P>

The use of the linear transformation method to systolize the Warshall algorithm for computing the transitive closure of a graph on a mesh-connected array (without wraparound connections) is discussed. The technique is extended to design linear systolic arrays. The advantage of this approach is easy verification of correctness, as well as synthesis of a family of arrays with tradeoffs between I/O bandwidth, number of processing elements, and local storage. The technique can be further refined to cope with problems that entail nonconstant dependency vectors.>