Abstract This article examines the resilience of different Apollonian network (AN) types—deterministic, random, and evolutionary—to systematic attacks. ANs, members of the family of maximal planar graphs, possess unique properties such as high clustering coefficients, small-world properties, scale-free behavior, Euclidean and space-filling properties, and modularity. These peculiarities require a thorough investigation of their robustness. This work presents a novel approach to studying ANs by implementing evolutionary Apollonian networks (EANs). These EANs include various probabilities distribution functions, including exponential, degenerate, logistic, Pareto, and stable (Cauchy, Lévy, Normal) distributions. To improve the robustness of these networks, we propose a novel edge rewiring mechanism using a genetic algorithm (GA). The GA aims to optimize a combined metric that includes the Flow Robustness of Degree (SFRD), Betweenness (SFRB), and Dangalchev's closeness (SFRC) centralities while preserving the original degree distribution and structural properties of the network. To evaluate the effectiveness of this approach, we use various robustness measures to assess the resilience of different AN types. The results show that SFRB, SFRD, and SFRC effectively rank ANs based on their robustness.

Magnetic tunnel junction (MTJ) with non-volatility, and near-zero leakage power features are believed to be the most prominent candidates for CMOS substitution. Logic-in-memory reduces the memory wall challenge and takes advantage of these features, but still has the challenge of writing to a magnetic device with regard to power consumption and device failure. Considering these challenges, we propose new designs in the approximate computing approach for magnetic device-based primitives. This paper proposes several power- and/or delay-efficient configurable Logic-in-Memory for Imprecise Tolerant Applications (LIMITA) based on spin transfer torque (STT) and STT-assisted voltage control magnetic anisotropy (VCMA) magnetic devices. Image processing is one of the most widely used imprecise tolerant applications with a high computational volume. Therefore, we map LIMITA with several approximation boundaries in Sobel, Sharpening, and Smoothing algorithms. To evaluate LIMITA at circuit and application levels, we did extensive simulations in HSPICE and MATLAB, respectively. Compared to the state-of-the-art works, the exact design of LIMITA improves the number of transistors in the logic tree up to 66% with 12% power overhead due to its configurability feature. In addition, in comparison with approximate primitives, LIMITA-$\text{F}_{\mathrm {i}}$improves delay, power consumption, and the number of transistors by$4.5\times$,$71.5\times$, and$2\times$respectively.

Because of high bandwidth, low latency and flexible topology configurations provided by wireless NoC, this emerging technology is gaining momentum to be a promising future on-chip interconnection paradigm. However, congestion occurrence in wireless routers reduces the benefit of high speed wireless links and significantly increases the network latency, therefore, in this paper, a Dynamic Application Mapping Algorithm (DAMA) is introduced for wireless NoCs in order to reduce both internal and external congestion. DAMA has three key steps: finding the first node to map, choosing the first task to be mapped onto the first node, and allocation of the remaining tasks to the remaining nodes. Simulation results show significant gain in the mapping cost functions compared to state-of-the-art works.

This paper presents a novel methodology to provide a promising solution for complex on-chip communication problems in order to reduce power consumption and delay. Our proposed reconfigurable Network-on-Chip (NoC) architecture is integrated with the radio frequency Interconnect (RF-I) with signal propagation at the speed of light. It is based on setting up express shortcut paths (ESPs) which include single-cycle multi-hop RF-I shortcut between selected pairs of NoCs cores. Hence, the packets belonging to distance nodes in the network can bypass intermediate routers while traveling through these ESPs. In this scheme, ESPs are constructed based on an energy model and performance constraints to accelerate critical communication path at the design time. Further, we also try to optimize these ESPs by using a novel flow control at a run time. Additionally, a suitable routing algorithm is suggested to support the packet to reach their destinations appropriately without struggling in congested paths. The experimental results captured by SoCs applications reveal that in comparison with the conventional NoC router, the proposed router takes 49% and 74% reduction in latency and energy, respectively besides 8.7% area overhead.

Talking out the network issues, the switching techniques specify the connection activities performed by the switching elements when a message is received at the input port. Traditional switching mechanisms such as Wormhole Switching (WS) realize high performance, but prone to deadlock in the vicinity of faults. While some techniques such as adaptive routing can alleviate the problem, it cannot solve the problem by itself. This has motivated the development of different switching techniques. The Scouting Switching (SS) has been suggested as an efficient switching mechanism for reconciling the confliction demands on communication performance and fault-tolerance in interconnection networks. Although SS has been around for years and it can greatly benefit from adaptive routing as it reduces blocking in the network, there has been hardly any attempt to provide an analytical model for SS when fully adaptive routing along with virtual channels is used. Besides, mesh is one of the most desirable topologies regarding to characteristics which can offer very good scalability. In an effort to fill this gap, this paper proposes the first analytical model for 2-D mesh networks using SS augmented with virtual channels. Experimental results show that this model is able to predict message latency with a good degree of accuracy.

A Multi-stage Interconnection Network (MIN) is one of the choices for Networks-on-Chip (NoCs) architecture designer for its simple topology and easy scalability with low degree. The evolution of digital design lies in the ability to shrink circuit size with each advance in process technology. As CMOS implementing technology continues to scale down, standard interconnect will become a major bottleneck for on-chip MIN platform performance. One of the nanoelectronic architectures that have been reorganized as one of the top six emerging technologies in future computers, known as Carbon NanoTube (CNT). CNTs have emerged as a promising material for future generation ICs. It is our purpose, in this paper, to present a comparative performance study for implementation of six prominent MINs (i.e., Omega, Butterfly, Baseline, Generalized Cube, Benes, and Clos networks) using CNT-based switches. The performance measures studied are compared to that of conventional CMOS in 16nm process technology and reflect a great deal of improvement in the network performance.

Multi-stage Interconnection Networks (MINs) are important hardware platforms in various applications due to increasing design complexity and cost. Further, they are generally accepted concepts for solving the problems related to on-chip communications. Carbon nanotube (CNT) is a promising candidate for future on-chip interconnects and electro-thermal applications due to its superior electrical and thermal properties. Although MINs have been around for many years and they can greatly benefit as they reduce costs and complexities in the network, there has been hardly any attempt to exploit the CNT characteristics to design and implementation of MINs. In an attempt to fill this gap, this paper presents a novel method for implementation of MINs using CNT-based interconnects. The performance evaluation of these networks is compared to that of conventional CMOS interconnect in 16nm process technology and reflect a great deal of improvement in network performance.

Fault-tolerance and network routing have been among the most widely studied topics in the research of parallel processing and computer networking. A fault- tolerant routing algorithm should guarantee the delivery of messages in the presence of faulty components. In this paper, we present a comparative performance study of nine prominent fault-tolerant routings in 2D wormhole-switched tori. These networks carry the software-based routing scheme which has been suggested as an instance of a fault-tolerant method widely used in the literature to achieve high adaptivity and support inter-processor communications in parallel computer networks due to its ability to preserve both communication performance and fault-tolerant demands in such systems. The performance measures studied are the throughput, average message latency, power, and average usage of virtual channels per node. Results obtained through simulation suggest two classes of presented routing schemes as high performance candidates in most faulty networks.

One of the key issues in the design of multiprocessors system-on-chip (MP-SoCs), multicomputers, and peer-to-peer networks is the development of an efficient communication network to provide high throughput and low latency and its ability to survive beyond the failure of individual components. Generally, the faulty components may be coalesced into fault regions, which are classified into convex and concave shapes. In this paper, we propose a mathematical solution for counting the number of common fault patterns in a 2-D mesh interconnect network including both convex (I-shape, II-shape, square-shape) and concave (L-shape, U- shape, T-shape, +-shape, H-shape) regions. The results presented in this paper which have been validated through simulation experiments can play a key role when studying, particularly, the performance analysis of fault-tolerant routing algorithms and measure of a network fault-tolerance expressed as the probability of a disconnection.

One of the fundamental problems in parallel computing is how to efficiently perform routing in a faulty network each component of which fails with some probability. This paper presents a comparative performance study of ten prominent adaptive fault-tolerant routing algorithms in wormhole-switched 2D mesh interconnect networks. These networks carry a routing scheme suggested by Boppana and Chalasani as an instance of a fault-tolerant method. The suggested scheme is widely used in the literature to achieve high adaptivity and support inter-processor communications in parallel computer systems due to its ability to preserve both communication performance and fault-tolerant demands in these networks. The performance measures studied are the throughput, average message latency and average usage of virtual channels per node. Results obtained through simulation suggest two classes of presented routing schemes as high performance candidate in most faulty networks.

Massively parallel computing systems are being built with hundreds or thousands of components such as nodes, links, memories, and connectors. The failure of a component in such systems will not only reduce the computational power but also alter the network's topology. The software-based fault-tolerant routing algorithm is a popular routing to achieve fault-tolerance capability in networks. This algorithm is initially proposed only for two dimensional networks (Suh et al., 2000). Since, higher dimensional networks have been widely employed in many contemporary massively parallel systems; this paper proposes an approach to extend this routing scheme to these indispensable higher dimensional networks. Deadlock and livelock freedom and the performance of presented algorithm, have been investigated for networks with different dimensionality and various fault regions. Furthermore, performance results have been presented through simulation experiments