This paper presents an effective digital calibration method based on Volterra neural network (VNN) for pipeline analog-to-digital converters (ADCs). Typically, the nonideality of pipelined ADCs results in dynamic nonlinear systems that are difficult to comprehensively calibrate. The proposed approach combines the strong nonlinear modeling capabilities of Volterra series with the adaptability of neural networks to accurately compensate for nonlinear distortions in pipeline ADCs. The effectiveness of VNN-based calibration is verified in MATLAB and ZYNQ-7000 FPGA. A 625-MS/s 12-bit pipeline ADC in 28 nm CMOS process is presented to verify the proposed calibration technique. The experimental results show that owing to the proposed powerful calibrator, the SFDR and SNDR achieve 79.8 dB and 60.7 dB at low frequencies, 74.3 dB and 59.1 dB at high frequencies, respectively.

This brief presents a digital calibration for pipelined analog-to-digital converters (ADCs) utilizing the cascaded nonlinearity correction (CNC) method. By cascading three correction layers for compensating nonlinearities in different parts of pipelined ADC, it comprehensively calibrates distortion in both ADC front end and back end with a low hardware cost. In addition, this work employs a discriminative fine-tuning least-mean-square (DFT-LMS) algorithm with varying step sizes for different layers, thereby improving both the convergence speed and the accuracy. An 800-MS/s, 12-bit ring amplifier-based pipelined ADC is presented to verify the proposed calibration technique. With calibration, the SFDR has a 26.7-dB improvement at low frequency and 23.6-dB improvement at Nyquist frequency, resulting in over 6-dB improvement compared with prior-art calibration techniques. The calibration algorithm has been verified on a TSMC 28-nm CMOS process. The experimental results show that the proposed ADC calibrator has an area of$6592~\mu $m2 and consumes 5.31 mW at 800-MHz clock rate.

In this paper, a fully digital calibration based on sinusoidal fitting (sine-fit) is proposed to overcome the difficulty of signal fitting in hardware implementation. The two-step frequency detection, grouping and recursive sine-fit method are proposed to address the trade-off between frequency estimation accuracy and hardware overhead. The simulation results in MATLAB and FPGA-based hardware verification are employed to demonstrate the performance and hardware overhead. A 400-MS/s 12-bit voltage-time hybrid pipeline ADC in a 28 nm CMOS process is presented to verify the proposed calibration technique, the simulation results show that the Nyquist-rate SFDR and SNDR are improved by 12.2 dB and 11.4 dB, respectively.

This paper presents a 400-MS/s 12-bit voltage-time hybrid pipeline ADC in a 28 nm CMOS process. The first stage is an asynchronous SAR ADC resolving 6 bits, and the second stage is a time-domain ADC composed of a VTC and a 7-bit SAR TDC (with 1-bit redundancy). To speed up the time domain operation, a ping-pong switching technique is used in the second stage. Besides, a common mode VTC is adopted to improve the linearity during the voltage-to-time conversion. A non-binary SAR TDC is also designed to tolerate the MSBs decision errors in the time-domain quantization. Furthermore, a LMS-based background calibration is performed to correct the capacitor mismatch error, interstage gain error, and bit-weight in the SAR TDC. The simulation results show that this design achieves a SNDR of 63.3 dB and a SFDR of 79.1 dB at Nyquist input. The power consumption is 9.6 mW with a supply of 0.9V, showing a FoM of 20.1 fJ/conversion-step.

This paper presents split attenuators combined with adjustable gain amplifiers as a two-stage time-gain compensation (TGC), such that it can extend the gain range of the Analog Front-end (AFE) for ultrasound image systems. To avoid artifacts caused by discrete gain control, continuous dB-linear gain varying with time is achieved by the split two-stage resistive voltage-divider attenuator whose attenuation value is decided by the MOSFET resistance which is inversely proportional to area. Rigorous theoretical analysis proves that placing the attenuators in the front and back stages of a programmable-gain amplifier (PGA) in the AFE as the proposed architecture demonstrated solves the contradiction between extending the gain range and saving area. The total attenuation range is broken down into two stages so that the system noise performance is optimized and unlike the prior single-stage-attenuator work, the dB-linearity is free from the negative impact of parasitic resistance introduced by area expansion. The proposed AFE has been fabricated by a 28-nm CMOS process, occupying 0.145 mm2 active area and consuming 75mW from a 2.5 V supply. It achieves a 74.7 dB adjustable gain range while providing a 15 MHz/30 MHz switchable bandwidth for all gain modes. The lowest input-referred noise (IRN) of the system was measured as 2.38 nV/$\sqrt {\mathrm {Hz}}$at 5MHz with the TGC reaching the highest gain.

A 2.5 GS/s12-bit 4-channel time-interleaved SAR-assisted pipelined ADC is proposed. The bias-enhanced ring amplifier serves as a residual amplifier offering high bandwidth and superior power efficiency over conventional operational amplifier. A high linearity front-end is proposed to mitigate the non-linearity of the ESD diode and provide sufficient driving ability. In addition, it can reject the kickback noise from the core ADC. A digital background calibration method with digital-mixing is adopted to fix the mismatches among channels. The measured SNDR/SFDR with a low-frequency of the prototype ADC are 51.0/68.0 dB, achieving a competitive FoMwof 0.48 pJ/conv.-step at 2.5 GS/s.

This paper presents a neural network-based digital calibration algorithm for high-speed and time-interleaved (TI) ADCs. In contrast with prior methods, the proposed work features joint amplitude-dependent and phase-dependent nonlinear distortion correction without prior-knowledge of ADC architecture feature. A dynamic calibration is first used to compensate for phase-dependent distortion. Two training optimizations, including a sub-range-sample-based batch schemes and a recursive foreground co-calibration flow are proposed to reduce the error and overfitting and further save hardware resources. A practical calibration engine is also investigated for interleaved ADCs with distributed weight and shared weight methods. To demonstrate the effectiveness of the method, the calibration engine is verified by two fabricated ADC prototypes, a 5 GS/s 16-way interleaved ADC and a 625 MS/s interleaving-SAR assisted pipeline ADC. Measurement results show that SFDR is improved between 16.9dB and 36.4dB before and after calibration for different frequency inputs. To trade-off between accuracy and power consumption, a quantized and pruned engine is implemented on both FPGA and 28nm CMOS technology. Experimental results show that the dedicated calibration on silicon consumes 8.64mW with 0.9V power supply at 333MHz clock rate. Measurement results show that the quantized hardware implementation has only 0.4-4 dB loss in SFDR.

Recently, the neural network has been applied to calibrate the successive-approximation-register and pipelined analog-to-digital converters (SAR-Pipelined ADCs), which requires no prior knowledge. However, the large hardware area of the full-precision neural network (FPNN) limits the promotion of this method. This paper proposes an optimization scheme called partially binarized and fixed neural network (PBFNN) to simplify the hardware through the following mechanisms. First, the multipliers that occupy a considerable area are optimized by binarization. Second, the fixed layer does not require training, hence saving the hardware for backpropagation. A 14-bit 60 MS/s ADC prototyped in 28-nm CMOS process is used to verify the PBFNN-based calibration. The measurement results show that the ADC achieves an SFDR of 95.0 dB and an ENOB of 10.6 bit. Compared with the previous scheme, the SFDR and ENOB are lossless. We also synthesize both schemes in Synopsys Design Compiler with a 28-nm library. The synthesis result indicates that the hardware area is optimized by 71.95%.

This paper presents an 11-bit 500 MS/s two-step SAR ADC with non-attenuated passive residue transfer for high-speed and high-resolution operations. The proposed partial interleaved CDACs scheme in the second stage reduces the parasitic capacitance for the first stage. The comparator reusing scheme avoids the complex calibration of each offset for multi-comparators. An edge-detected calibrator is adopted to achieve low power and a constant calibrated voltage in the calibration of interstage gain error and offset. The prototype is implemented in 28 nm CMOS process. The simulation shows that the proposed ADC achieves an SNDR of 61.98 dB and an SFDR of 81.73 dB at Nyquist input at 0.9-V supply. The power consumption is 3.06 mW, showing the FoM of 5.58 fJ/con-step.

This paper presents a single-coarse dual-fine architecture that improves energy-efficiency of pipelined-SAR analog-to-digital converters (ADCs). A coarse and fast sub-ADC is used to quantize the most significant bits (MSBs), which are encoded with a proposed residue transformation method to control the residue generation of the first stages in two fine channels. The residue voltages generate on the capacitive digital-to-analog converters (C-DACs) of split fine channels directly without successive approximation processes. Therefore, the conversion rate is increased and the power is reduced. A shuffle mechanism is introduced into split-ADC based digital background calibration to avoid the divergence of the conventional algorithm in the proposed architecture. A high-energy-efficiency dynamic amplifier is also introduced as the residue amplifier. A 14-bit 60-MS/s ADC is prototyped in a 28-nm CMOS process. The digital calibration engine operates under 0.9-V supply, other parts of the ADC core operate under 1.05-V supply. The ADC core consumes 4.26 mW. Measurement results show that the calibration improved the signal-to-noise and distortion ratio (SNDR) and spur-free dynamic range (SFDR) dramatically, the calibrated ADC achieves SNDR and SFDR of 66.9 dB and of 91.0 dB respectively, translating to a Schreier FoM of 165.4 dB and a Walden FoM of 39.3 fJ/conversion-step.

A 13 bit 100 MS/s successive approximation register analog-to-digital converter (SAR ADC) is presented for high-resolution and high-speed applications. In order to reduce comparator noise and improve the speed of comparator, a three-stage comparator based on the inverter is proposed. To reduce the leakage current of the low-Vt transistor, an improved asynchronous control logic with feedback is proposed. An energy-efficient SAR ADC with high sampling rate can be realized with these techniques combined. The prototype is implemented in SMIC 14-nm CMOS FinFET. Simulation result with noise, parasitic capacitance, and other non-ideal effects shows that ADC achieves a low input frequency SNDR/SFDR of 75.13/89.48dB, while the SNDR/SFDR at Nyquist is 74.57/84.42dB without any calibration. The prototype consumes 2.34mW from 0.8-V supply, leading to a Walden figure-of-merit 5.22fJ/conversion-step at Nyquist.

A 13-bit SAR ADC with bridged capacitor array is implemented. In order to calibrate the weight error due to parasite and mismatch. A weight redundant structure and a one-by-one foreground weight estimate scheme is proposed. A dithering mode can improve the dynamic performance further. A prototype is fabricated in a 28nm CMOS technology. The measurement of the ADC with conversion rate of 180MS/s achieves an SFDR of 79.1dBc and an SNDR of 64.3dBc, with remarkable improvement after calibration and dither.

One main concern for a continuous-time (CT) multi-stage noise-shaping (MASH) delta sigma (ΔΣ) analog to digital (ADC) is how to make the digital filtering responses match the analog transfer functions of the sub-loop. Since non-ideal factors of CTΔΣ modulator greatly affect analog transfer functions, the accurate estimation of the signal transfer function (STF) and quantization noise transfer function (NTF) affects the final performance of the ΔΣ ADC. In this paper, STF and NTF are simultaneously estimated for CT MASH 0-3-0 ΔΣ ADC with autoregressive and moving-average (ARMA) Model. The proposed method called digital quantization noise leakage reduction algorithm (DQNLRA) could also deal with excess-loop-delay (ELD) and finite gain and bandwidth of op-amp in CTΔΣ modulator.

This paper presents a high linearity dynamic amplifier with an on-chip gain detection technique, which realizes the stabilization of process, voltage, and temperature (PVT) with the real-time fluctuation. Based on the cross-coupled capacitive degeneration topology and characteristics of transistors in weak inversion, according to the simulation results, the proposed dynamic amplifier achieves -80 dB total harmonic distortion (THD) across the wide range of supply voltage and temperature. The prototype amplifier is designed at the supply voltage of 1 V in 28 nm CMOS process, and it dissipates 260 μW at the frequency of 100 MS/s with the maximum output swing of 1.2 Vpp. The power consumption is positively related to the clock frequency.

In this paper, a novel modified Nauta OTA has been proposed for achieving temperature independent property. A tuning voltage is applied to the bodies of the differential input PMOS transistors, resulting in the variable threshold voltage of the transistors and then changing the transconductance of the Nauta OTA. And a high precision bandgap reference is used for generating a proportional to absolute temperature (PTAT) voltage to monitor the temperature of the chip. The proposed Nauta transconductor is implemented in TSMC 65-nm standard CMOS process. Simulation results show that the transconductance tunability performs less than 0.1% over the temperature range of -40 °C to 120 °C. This method is demonstrated that temperature variation has slight influence on the transconductance fluctuation after accurate trimming.

Parasitic attenuation, memory effect and channel-length modulation limit the linearity of the state-of-the-art CMOS integrated ADC input buffer, this paper introduces an operational amplifier assisted input buffer that improves the linearity. A bootstrapped switch with improved linearity is also presented. Simulation results show that the proposed input buffer achieves an averaged SFDR improvement of 15dB in the first Nyquist zone. The proposed bootstrapped switch achieves 8.8dB SFDR improvement near Nyquist input frequency compared to the conventional circuit. The proposed techniques improved the linearity of the sampling front-end significantly.

A SAR assisted pipeline ADC with an inter-stage ring amplifier is an energy efficient structure. The ring amplifier is an alternative to an OTA for its low power consumption and large output swing. To improve the accuracy of the common-mode feedback circuit and speed up the settling of the ring amplifier, an improved bias-enhanced ring amplifier is proposed. Additionally, to alleviate the loss of the ring amplifier's DC gain in the nanoscale CMOS process and to migrate the dynamic offset caused by the non-ideal switches, a gain error cancellation method is introduced by adding a feedforward amplification path. Designed in a 1 V 28 nm CMOS process, two cascaded pipeline stages and two time-interleaved SAR sub-ADCs make up the ADC. In the post layout simulation that includes transient noise and other non-ideal factors, this 12-bit ADC achieves 60.9dB SNDR and 72dB SFDR at a Nyquist input and sampled at 800 MS/s without analog cancellation, consuming 16.02mW. With gain error cancellation, SFDR is improved by more than 3dB.

A 100MS/s 12-bit SAR ADC designed for terahertz imaging sensor is presented. The proposed ADC utilizes coarse-fine SAR architecture to relax reference requirement and improve operation rate. Split-CDAC structure is applied to reduce chip area, and its LSBs capacitors are reused as a coarse DAC. Redundant capacitor arrays are applied in both coarse and fine ADCs. A power-and-area-efficient ADC with high sampling rate can be realized with these techniques combined. The prototype is implemented in TSMC 1P9M 65nm-CMOS process. The simulation result with noise and other on board non-ideal effects shows that the ADC consumes 1.8 mW with an SNDR 65.7 dB and an SFDR of 77.0 dB with a Nyquist input at 1.2V power supply, achieving an ENOB of 10.6-bit and a FoM of 11.6 fJ/conv-step.

A split-based background calibration technique for pipelined-ADC is proposed in this brief to handle both capacitors' mismatches and non-linearity of residue amplifiers in multiple pipeline stages. Some concepts and approaches of machine learning, say multilayer perceptron and backpropagation algorithm, are introduced to deal with the problems appearing in modeling and solving the nonlinear calibration filter. Computer simulations demonstrate an exaltation of both SNDR and SFDR for more than 50dB in a 15-bit 7-stages pipelined-ADC with non-ideal first three stages.

This paper presents an 11bit 200MS/s SAR-assisted pipeline ADC with a 2.5bit front end stage and two time-interleaved 9bit sub-SAR ADCs, implemented in 65nm CMOS process. The bias-enhanced ring amplifier works as the residue amplifier for power efficiency and large signal swing. Two self-biased inverter stages are designed in the ring amplifier to maintain the closed loop stability. The SAR ADCs with custom capacitor arrays are featured by l.5bit acceleration in the second quantization step. With the least-mean-square algorithm calibration, this ADC achieves an ENOB of 9.5bit and a FoM of 15.7fJ/conv-step at a 2.4MHz input signal sampled at 200MHz.

This brief presents a 7-bit 700-MS/s four-way time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC). A partial Vcm-based switching method is proposed that requires less digital overhead from the SAR controller and achieves better conversion accuracy. Compared with switchback switching, the proposed method can further reduce the common mode variation by 50%. In addition, the impacts of such a reduction on the comparator offset, noise, and input parasitic are theoretically analyzed and verified by simulation. The prototype fabricated in a 65-nm CMOS technology occupies an active area of 0.025 mm2. The measurement results at the 700 MS/s sampling rate show that the ADC achieves signal-to-noise-and-distortion ratio of 40 dB at Nyquist input and consumes 2.72 mW from a 1.2 V supply, which results in a Walden FoM of 48 fJ/conversion step.

Protein folding is critical for many biological processes. In this work, we propose an NoC-based multi-core platform for protein folding computation. We first identify the speedup bottleneck for applying conventional genetic algorithm on a mesh-based multi-core platform. Then, we address this computation- and communication- intensive problem while taking into account both hardware and software aspects. Specifically, we group the processing cores into islands and propose an NoC-based multicore architecture for intra- and inter-island communication. The high scalability of the proposed platform allows us to integrate from 100 to 1200 cores for the folding computation. We then propose a genetic migration algorithm to take advantage of the massive parallel platform. Our simulation results show that the proposed platform offers near-linear speedup as the number of cores increases. We also report the hardware cost in area and power based on a 100-core FPGA prototype.

This paper presents a new low offset comparator with a mismatch-suppressed dynamic preamplifier Various mismatches contribute to comparators's input referred offset. The proposed mismatch suppression is achieved by sampling the mismatches at the dynamic preamplifier's output node during the precharge phase. A time-domain analysis method is utilized to quantize the suppression effects. By the techniques, a 1-GS/s four-input comparator is implemented by 65-nm CMOS technology. It achieves a 60-μW power dissipation and a 1.89-mV 1-sigma(σ) offset voltage, which is a 90% improvement compared to its non-suppressed counterparts.

A 400-MS/s 8-b SAR ADC with 2-b/cycle conversion is presented in this paper. Compared with conventional SAR structure, an AUX-DAC is proposed to achieve high switch energy efficiency and low power. The proposed structure of ADC uses a shared interpolator, which not only reduces one DAC, but also separates the input signal from the comparator to reduce the kickback noise. To further increase the speed, the logic delay is reduced by the comparators working alternatively and the results directly sent to the M-DAC. Foreground calibration is used to calibrate the offset of the comparators. The post simulation results show that the ADC achieves a SNDR of 48dB, power consumption of 5.6mW and FoM of 67fF/conversion-step at 400MS/s rate with 1.2 V supply voltage.

In this paper, an output-dependent delay cancellation (ODDC) technique is proposed. For a high-accuracy digital-to-analog converter (DAC), the delay differences caused by output voltage is one of the major nonlinearities that deteriorate the dynamic performance. The ODDC technique has the advantages of significant improvement on the dynamic performance in a wide frequency range without increasing the noise floor. ODDC can eliminate the switching time variations caused by output voltage of DAC through tuning the bulk voltage of switches in the deep N-well. The algorithm of ODDC technique is derived. To verify the implementation, a 14 bits 400MS/s current-steering DAC with ODDC is simulated and the SFDR can be improved by about 12dB with proper circuit parameters.

A Nyquist-rate time-interleaved current-steering digital-to-analog converter (DAC) with dynamic channel matching (DCM) is proposed. Thanks to the proposed Nyquist- rate time-interleaved architecture, the DAC can properly operate at more than lGS/s for a near-Nyquist output signal. The key limitation of the time-interleaved architecture is the mismatches between channels. The proposed DCM method can be applied to significantly suppress the spurious tones caused by imperfect channel matching. A 14-bit 1 GS/s current-steering DAC with behavior models and a 0.18μm CMOS technology is simulated to illustrate the wideband time-interleaved architecture and the harmonic elimination of the DCM.

This paper presents the design of a sideband-suppressed synthesizer for dual-carrier MB-OFDM transceivers covering 11 frequency bands from 6.2GHz to 9.4GHz and 3 frequency bands from 4.2GHz to 4.8GHz, each with a bandwidth of 264MHz. Careful band plan is made to minimize the complexity. The synthesizer generates 14 carrier frequencies from a single frequency source. Improvements are made to the circuits to further suppress the sidebands. The synthesizer chip is designed with TSMC's 0.13-μm RF CMOS technology. The circuit draws a current of 42mA from a 1.2V supply. It achieves a sideband rejection of 45dBc and a phase noise of -105dBc/Hz@1MHz.

This paper presents a 10-bit 40-MS/s pipelined ADC in a 0.13-μm CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency compensation is developed to achieve both high bandwidth and large swing with low power dissipation. The measured result shows that the ADC achieves over 77 dB SFDR and 57.3 dB SNDR within the first Nyquist zone and maintains over 70 dB SFDR and 55.3 dB SNDR for input signal up to 75 MHz. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.2 LSB and ±0.3 LSB respectively. The ADC consumes 15.6 mW at the sampling rate of 40 MHz from a 1.2-V supply voltage, and achieves a FOM value of 0.22 pJ/step.

In this paper, we investigate the analog front-end imperfection in multi-band orthogonal frequency division multiplexing (MB-OFDM) ultra-wideband (UWB) systems and propose a joint estimation and compensation scheme. The estimation of CFO and SFO is presented on frequency domain, which is robust to frequency dependent I/Q imbalance. After that, I/Q imbalance and channel response is jointly estimated with partial compensation to CFO and SFO. Finally, pilot sub-carriers within OFDM symbols are used to track the residual phase distortion. Simulation results show that the proposed joint estimation and compensation scheme achieves 0.3dB SNR advantage in practical MB-OFDM UWB systems comparing to traditional joint estimation algorithm.

A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters to create the class-AB behavior in the first and second stages. With this structure, the transconductances (gm) of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode Miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results present the sample-and-hold (S/H) of the 11-bit 40-MHz pipelined ADC using the proposed amplifier consumes only 5.5 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio(SNDR) 78.78 dB, spurious-free dynamic range (SFDR) 87.2 dB and total harmonic distortion (THD) -85.9 dB with 19.1 MHz full-swing input signal.

This paper presents a field-programmable gate array (FPGA) implementation of a new multiple-input multiple-output (MIMO) signal detection algorithm applicable to ultra-high throughput MIMO communication systems. The algorithm simplifies the computation significantly compared to traditional K-Best algorithm, and with negligible bit error ratio (BER) degradation. A highly-parallel structure is implemented on the Xilinx Virtex-4 (XC4VLX200) platform, which achieves 2.2 Gbps detection throughput and is about four times over previous implementation. Moreover, a pre-processing method is realized to reduce the number of multipliers inside the detector and shrinks the critical path delay down to 6.79 ns. Together with candidate-sharing-architecture to further save the hardware cost, a high speed, compact signal detector for MIMO systems is demonstrated.

A new 8PBF structure for 64/128 flexible point FFT processor is proposed. The processor, which is based on 8*8*2 mixed radix algorithm, can deal with multiple inputs more efficiently for MIMO applications. The 8PFB structure efficiently brings the throughput of the processor up to 1GS/s and the chances of register reverse down, reducing the power dissipation remarkably. Meanwhile the modified shift-add algorithm can remove complex multipliers in the FFT processor.

This paper presents the design of a Viterbi decoder for the multiband OFDM (MB-OFDM) ultra-wideband (UWB) communication systems. To achieve the highest data rate desired with hardware efficiency, a folded sliding block architecture is utilized. For lower data rates, some of the processing elements (PE) in the Viterbi decoder are disabled to save power. The design has been implemented on FPGA and the throughput can be up to 432 Mbps on a Xilinx Virtex-4 device.

In OFDM-based UWB baseband, synchronizer plays a key role to the performance of the whole system. Therefore achieving an area and power efficient architecture at least SNR loss becomes the main challenge of synchronizer design. To meet 528Msamples/s throughput, the parallel architecture is used in current approaches. But it leads to higher area and power consumption. In this paper, we propose an efficient synchronizer for OFDM-based UWB system, consisting of the filter-free symbol synchronizer, frequency synchronizer with improved Moose algorithm and sign-based auto-correlator. According to the results of synthesis using SMIC, 0.13μm CMOS process, the proposed design can achieve the throughput requirement with only 24% gate count and 25% power consumption (in idle state) of the conventional four-parallelism approach.

A frequency synthesizer applied to 1000Base-T Ethernet transceiver as well as 10/100Base-T mode is described. A dynamic voltage-mode phase interpolator is used and a more precise analysis and calculation on degressive interpolating resistors are given. The design not only meets the transmitter's requirement of very accurate rising (falling) edge control but also offers much finer time-interval clocks compared to VCO natural multi-phase outputs. The chip was implemented in SMIC 0.18-/spl mu/m standard CMOS technology and achieves an RMS jitter of 11ps with the crystal oscillator reference RMS jitter of 16ps. The power is smaller than 4mW from a 1.8V power supply in all modes.