Self-regulated learning significantly influences students’ academic behavior and performance. Traditional SRL assessment heavily relies on subjective and self-evaluation methods, which are susceptible to personal biases and cognitive limitations. In this study, we leverage mobile devices with GPS and sensors to collect self-reported and passive mobile sensing data from 211 college students over a year. Our aim is to conduct a passive assessment of self-regulated learning. To achieve this, we apply four deep learning models to analyze behavioral features associated with self-regulated learning using students’ life record data. Our findings demonstrate a precise assessment of student self-regulated learning, encompassing the following subscales. Environment structuring (MAE = 2.88, r = 0.54) represents participation in the organization and construction of the learning environment. Time management (MAE = 2.82, r = 0.57) represents planning study time and balancing study with other activities; Help seeking (MAE = 4.86, r = 0.53) represents the tendency and frequency of students to seek help during the learning process. Our study helps inspire new forms of education to assess self-regulated learning and paves the way for individualized interventions in future studies. • We develop and implement the iSense system for SRL assessment. • Collecting mobile sensing and self-reported data from 211 students over a year. • Establishing an SRL assessment model using mobile sensing data and deep learning. • We observe that SRL highly correlates with app usage patterns and sensing data. • Our study can achieve longitudinal monitoring and early intervention of SRL.

Understanding and identifying the nature of learner confusion is important for online learning platforms. In this study, we address this problem by analyzing forum posts from large-scale online courses. However, due to the large volume of comments and frequent interactions, confusion posts are often overlooked. Existing methods and models, while capable of detecting confusion, typically rely on linguistic features of posts and community factors (e.g. votes, views) but ignore personalized contexts, such as the specific causes and types of confusion. To address this problem, we create the first deep learning dataset focused on confusion types and develop a BERT-based network to model personalized features and identify confusion types. Considering the highly imbalanced distribution of different types of confusion, we further design a novel loss function that adaptively optimizes the training weights for each type. Our method’s effectiveness is confirmed through extensive experimentation.

Hierarchical Text Classification (HTC) organizes candidate labels into a hierarchical structure and uses one or more paths within the hierarchy as the ground-truth labels, which has been applied to various downstream tasks, e.g., sentiment analysis and harmful text detection. Existing works often involve data-driven models that are trained on large-scale datasets. However, creating annotated datasets is labor-intensive and time-consuming. To address this issue, recent work has focused on the few-shot HTC task, where each class has only a few samples, e.g., 5. These approaches perform classification at each layer separately and leverage the prompt learning capability of pre-trained models like BERT. However, we find that these methods always neglect the inter-layer relationships. To solve this problem, we propose a new model called Bidirectional Path Constraint by Label Weighting ( Bpc-lw ). Its basic idea is to use a pre-defined label embedding matrix and a feed-forward neural network for information propagation between layers, while also designing a bidirectional label weighting method to constrain the predictions of each layer to be along the same path in the label hierarchy. In addition, we employ a contrastive learning-based method to enhance the discriminative capacity of the hierarchical embeddings. We compare our proposed method with recent few-shot HTC baseline models across 3 benchmark datasets, and the experimental results demonstrate the effectiveness of Bpc-lw . • We argue that current methods neglect inter-layer information propagation. • We design label embedding matrices and feed-forward neural networks to transmit the label features. • Extensive experiments are conducted.

Emotion-cause pair extraction (ECPE) main focus is on extracting all potential emotion clauses and corresponding cause clauses from unannotated documents. Existing methods achieve promising results with the help of fine-tuning and prompt paradigms, but they present three downsides. First, most approaches cannot distinguish between the emotion-cause pairs that belong to different types of emotions, limiting the existing approaches’ applicability. Second, existing prompt methods utilize a one-to-one mapping relation to achieve label words to category mapping, which brings considerable bias to the results. Third, existing methods achieve the cause extraction task supported by explicit semantic understanding or basic prompt templates, ignoring the implicit information contained in the cause clauses themselves. To solve these issues, we propose an Emotion knowledge-aware Prompt-tuning for Emotion-Cause Pair Extraction (EmoPrompt-ECPE) method, which integrate the knowledge of emotion categories in the ECPE task and mine the implicit knowledge of cause clauses. Specifically, we inject the latent knowledge of the cause clauses and the emotion types into the prompt template. Besides, we extend the emotion labels for many-to-one mapping of label words to categories with an external emotion word base. Furthermore, we utilize the cosine similarity filtering of the label word base to reduce the noise caused by knowledge introduction. Experiments on both Chinese and English benchmark datasets show that our approach can achieve state-of-the-art results. Our code and data can be found at: https://github.com/xy-xiaotudou/EmoPrompt-ECPE.

Abstract The evergrowing Internet of Things (IoT) ecosystem continues to impose new requirements and constraints on every device. At the edge, low-end devices are getting pressured by increasing workloads and stricter timing deadlines while simultaneously are desired to minimize their power consumption, form factor, and memory footprint. Field-Programmable Gate Arrays (FPGAs) emerge as a possible solution for the increasing demands of the IoT. Reconfigurable IoT platforms enable the offloading of software tasks to hardware, enhancing their performance and determinism. This paper presents ChamelIoT, an agnostic hardware operating systems (OSes) framework for reconfigurable IoT devices. The framework provides hardware acceleration for kernel services of different IoT OSes by leveraging the RISC-V open-source instruction set architecture (ISA). The ChamelIoT hardware accelerator can be deployed in a tightly- or loosely-coupled approach and implements the following kernel services: thread management, scheduling, synchronization mechanisms, and inter-process communication (IPC). ChamelIoT allows developers to run unmodified applications of three well-established OSes, RIOT, Zephyr, and FreeRTOS. The experiments conducted on both coupling approaches consisted of microbenchmarks to measure the API latency, the Thread Metric benchmark suite to evaluated the system performance, and tests to the FPGA resource consumption. The results show that the latency can be reduced up to 92.65% and 89.14% for the tightly- and loosely-coupled approaches, respectively, the jitter removed, and the execution performance increased by 199.49% and 184.85% for both approaches.

Deep learning algorithms perform poorly on long-tailed datasets because there is insufficient data in the tail classes to recover its original distribution, resulting in an under-representation of the tail classes in the model. In this work, we propose H2T-FAST, a Head-to-Tail Feature Augmentation method by Style Transfer to improve the performance of the tail. H2T-FAST has the following advantages: (1) It is a fast and universal method that acts on the feature space and so, it can be applied to different backbone networks as well as easily integrated into various imbalanced algorithms with stable performance gains; and (2) it is used only in the training phase and therefore, imposes no additional burden on the deep neural network in the testing phase. In particular, we firstly and randomly select the same number of head samples as the tail ones in each training mini batch. Secondly, the style of the head is transferred to the tail to generate new tail data containing the head style, as a way to increase the number of the tail and get better feature representations. We test our methods on several benchmark vision tasks with state-of-the-art performances.

Sorting is essential for many scientific and data processing problems. It is significant to improve the efficiency of sorting. Taking advantage of specialized hardware, parallel sorting, e.g., sorting networks and linear sorters, implements sorting in lower time complexity. However, most of them are designed based on the parallelization of algorithms, lacking consideration of specialized hardware structures. In this article, we propose an extended nonstrict partially ordered set-based configurable linear sorter on field-programmable gate arrays (FPGAs). First, we extend nonstrict partial order to the binary tuple and n-tuple nonstrict partial orders. Then, the linear sorting algorithm is defined based on them, with the consideration of hardware performance. It has 4N/n time complexity varying from 4 to 2 N as the tuple size varies. The number of comparisons reduces to N/2 in binary tuple-based sorting, which is half of the state-of-the-art insertion linear sorting. Finally, we implement the linear sorter on FPGAs. It consists of multiple customizable micro-cores, named sorting units (SUs). The SU packages the storage and comparison of the tuple. All the SUs are connected into a chain with simple communication, which makes the sorter fully configurable in length, bandwidth, and throughput. They also act the same in each clock cycle, so that the achieved frequency of the sorter improves. In our experiment, the sorter achieves at most 660-MHz frequency, 5.6 Gb/s throughput, and 87 times speed-up compared with the quick sort algorithm on general processors.

Computer Vision is an emerging field with diverse applications which encompasses many algorithms with heavy computations. Histogram of Oriented Gradients-Support Vector Machine (HOG-SVM) is one such versatile algorithm used for object detection and image classification despite it's heavy computation load. Processing such an algorithm in real time with adequate throughput is a challenging task for a general purpose processor. Moreover, an embedded CPU with very limited processing power could least cater such heavy processing. Therefore our research in general focuses on developing application specific architectures for hardware acceleration of computer vision algorithms. This paper presents a continuation of a series of research to hardware accelerate HOG-SVM algorithm on FPGA. In this paper we mainly present the high performance application specific architecture for hardware acceleration of HOG-SVM which was successful in achieving a high throughput of 240fps on HD frames of size 1920x1080 which is a significant improvement of performance compared to previous research. On the other-hand, both hardware utilization and power consumption are minimized. A mechanism based around Block RAM (BRAM) structures and deep pipelining are used as the key architectural techniques of achieving high performance. The proposed design was deployed on Zynq 7000 FPGA platform which contains a hardwired ARM CPU along with the programmable FPGA fabric. The accelerator is deployed on the FPGA and integrated with the ARM CPU using AXI memory interfaces. A hardware thread model and bare-metal device drivers were developed which encapsulate the behavior of the accelerator as a hardware thread to the applications running on the ARM CPU.

Computer systems are permanently present in our daily basis in a wide range of applications. In systems with mixed-criticality requirements, e.g., autonomous driving or aerospace applications, devices are expected to continue operating properly even in the event of a failure. An approach to improve the robustness of the device's operation lies in enabling fault-tolerant mechanisms during the system's design. This article proposes Lock-V, a heterogeneous architecture that explores a Dual-Core Lockstep (DCLS) fault-tolerance technique in two different processing units: a hard-core Arm Cortex-A9 and a soft-core RISC-V-based processor. It resorts a System-on-Chip (SoC) solution with software programmability (available trough the hard-core Arm Cortex-A9) and field-programmable gate array (FPGA) technology, taking advantages from the latter to support the deployment of the RISC-V soft-core along with dedicated hardware accelerators towards the realization of the DCLS.

With predictions pointing to more than 20 billion Internet-enabled 'things' by 2020 and much more to come, smart sensor nodes are expected to be predominant in the Internet of Things (IoT) era. As these systems are connected to the Internet and tend to implement an ever-growing number of mixed-criticality features, there is huge pressure for strong isolation to guarantee a reliable, secure, and predictable infrastructure. While virtualization has been a game-changer for consolidation and isolation in mid-to high-end embedded applications, for low-end and low-cost systems it is still in its infancy, and only a limited number of solutions have been proposed so far. This work aims at developing a lightweight hypervisor which provides strong isolation on resource-constrained devices. Our approach leverages TrustZone technology available on modern Arm microcontrollers (TrustZone-M) to implement a predictable virtualization infrastructure for low-end and low-cost systems. Experiments conducted on an Arm Musca-A multi-core platform demonstrate our solution achieves low memory footprint, high efficiency, and strict timing predictability.

This letter proposes ChamelIoT, an agnostic operating system (OS) framework for reconfigurable Internet of Things (IoT) devices. ChamelIoT is bringing a reconfigurable hardware OS stack supported by a semantically enriched infrastructure that aims at offering an easy-to-use tool for building (mainly) low-power and low-cost IoT sensors with performance, real-time, and power consumption advantages.

Approaches to Dynamic Binary Translation (DBT) on resource-constrained embedded systems are not straight forward, leading to several improvements and acceleration suggestions that rely on dedicated hardware. Software to hardware of-floading is a common acceleration procedure used when software-only approaches do not meet the performance requirements, making such approach suitable to be successfully applied to DBT. This article approaches hardware offloading to address some limitations of an in-house DBT engine, the DBTOR, regarding its Translation Cache (TCache) management mechanism. The suggested approaches are non-intrusive to the target architecture, which cope with the commercial-off-the-shelf (COTS)-driven deployment of DBT for the resource-constrained embedded devices. This work proposes a TCache management hardware module that overpasses the linked list and hash table software-only approaches, resulting in a performance improvement of 25% and 26%, respectively.

The Internet of Things (IoT) is revolutionizing the Internet of the future and the way smart devices, people, and processes interact with each other. Challenges in endpoint devices (EDs) communication are due not only to the security and privacy-related requirements but also due to the ever-growing amount of data transferred over the network that needs to be handled, which can considerably reduce the system availability to perform other tasks. This paper presents an IPv6 over low power wireless personal area networks (6LoWPAN) accelerator for the IP-based IoT networks, which is able to process and filter IPv6 packets received by an IEEE 802.15.4 radio transceiver without interrupting the microcontroller. It offers nearly 13.24% of performance overhead reduction for the packet processing and the address filtering tasks, while guaranteeing full system availability when unwanted packets are received and discarded. The contribution is meant to be deployed on heterogeneous EDs at the network edge, which include on the same architecture, field-programmable gate array (FPGA) technology beside a microcontroller and an IEEE 802.15.4-compliant radio transceiver. Performed evaluations include the low FPGA hardware resources utilization and the energy consumption analysis when the processing and accepting/rejection of a received packet is performed by the 6LoWPAN accelerator.

Virtualization technology starts becoming more and more widespread in the embedded systems arena, driven by the upward trend for integrating multiple environments into the same hardware platform. The penalties incurred by standard software-based virtualization, altogether with the strict timing requirements imposed by real-time virtualization are pushing research towards hardware-assisted solutions. Among existing commercial off-the-shelf (COTS) technologies, ARM TrustZone promises to be a game-changer for virtualization, despite of this technology still being seen with a lot of obscurity and scepticism. In this paper we present a Lightweight TrustZone-assisted Hypervisor (LTZVisor) as a tool to understand, evaluate and discuss the benefits and limitations of using TrustZone hardware to assist virtualization. We demonstrate how TrustZone can be adequately exploited for meeting the real-time needs, while presenting a low performance cost on running unmodified rich operating systems. While ARM continues to spread TrustZone technology from the applications processors to the smallest of microcontrollers, it is undeniable that this technology is gaining an increasing relevance. Our intent is to encourage research and drive the next generation of TrustZone-assisted virtualization solutions.

With the increased complexity of low-end devices in the Internet of Things (IoT), mainly due to the connectivity and interoperability requirements, the development and configuration of embedded operating systems (OSes) for such devices is not straight forward. The complexity of the communication requirements is usually mitigated by the OS, e.g., the Contiki-OS, as it already incorporates an IoT-compliant network stack. Yet, the configuration of such stack requires major knowledge on the code structure, leading to additional development time, particularly when the network comprises several wireless nodes and individual configurations with subsequent firmware that needs to be generated. Based on a developed software modeling domain-specific language, this paper presents the EL4IoT framework. It aims to reduce and ease the development time by promoting a design automation tool that can configure, and automatically generate code (ready to compile) for low-end IoT devices running the Contiki-OS. Although leveraging the whole Contiki-OS modeling, this work only refactored and modeled the network stack while approaching the OS itself as one big building block or component. The proposed approach can be extended to other IoT-enabled OSes as well as integrated in other design automation tools.

Virtualization technology is well established in the server and desktop spaces, and has been spreading across embedded system market. This technology allows for the coexistence and execution of multiples operating systems on top of the same hardware platform, with proven technological and economic benefits. Hardware extensions for easing virtualization have been added into several commercial off-the-shelf processors. Among existing technologies, ARM TrustZone is gaining particular attention due to its broadly availability into ARM processors. However, existent TrustZone-assisted virtualization solutions are limited to a dual-guest and single-core configuration, which can lead to the starvation of the non-secure side when the secure world does not yield the processor. This work presents the extension of a TrustZone-assisted hypervisor to an asymmetric multi-processing configuration. We describe and demonstrate how to run a general-purpose operating system side-by-side with an real-time operating system in a Xilinx Zynq-based platform, enhanced with a dual ARM Cortex-A9. The achieved results demonstrate that the implemented multicore approach not only completely eliminates starvation, but also increases the general-purpose operating system's performance, especially when the real-time workload is demanding.

Industrial solutions design is a highly complex topic due to the challenge of integrating multiple technologies into a single solution, the inherent complexity of the problems to be solved and also because the proposed solutions often require a great level of interoperability among their components and also the outside world. Dynamic Binary Translation has been used as a tool to deal with such interoperability issues, e.g., legacy support, virtualization and secure execution, among others. However its integration in the industry as an end-product is hampered by the intricate variability management required in this subject. To address these issues and in an attempt to power DBT utilization as an interoperability-providing tool, we propose a model-driven DSL modeling language for DBT architectures. The developed DSL proved to be efficient to model an in-house DBT engine, and MODELA DBT, a framework for ready-to-use DBT solutions was obtained. MODELA DBT provides design validation, easy configuration of customizable DBT parameters and components, as well as code generation features.

In the near future, billions of new smart devices will connect the big network of the Internet of Things, playing an important key role in our daily life. Allowing IPv6 on the low-power resource constrained devices will lead research to focus on novel approaches that aim to improve the efficiency, security and performance of the 6LoWPAN adaptation layer. This work in progress paper proposes a hardware-based Network Packet Filtering (NPF) and an IPv6 Link-local address calculator which is able to filter the received IPv6 packets, offering nearly 18% overhead reduction. The goal is to obtain a System-on-Chip implementation that can be deployed in future IEEE 802.15.4 radio modules.

Most hypervisors today rely either on (1) full virtualization on high-end hardware (i.e., hardware with virtualization extensions), (2) paravirtualization, or (3) both. These, however, do not fulfill embedded systems' requirements, or require legacy software to be modified. Full virtualization on low-end hardware (i.e., hardware without virtualization extensions), on the other end, has none of those disadvantages. However, it is often claimed that it is not feasible due to an unacceptably high virtualization overhead. We were, nevertheless, unable to find real-world quantitative results supporting those claims.

This paper focuses on the challenges faced when developing modern power electronic converters towards the concept of tomorrow's smart grids. Industrial and commercial electronic devices are nonlinear loads by nature and so they absorb non-sinusoidal currents and usually a chump of reactive energy. The presence of such loads raises power quality problems at installation sites as well as in the distribution system. Research has been focused on the electronic converters to improve electrical waveform quality, in particular, on shunt active power filters which are suitable to compensate current harmonics. In this paper, a shunt active power filter with an integrated Hardware/Software Digital Controller based on the p-q Power Theory is presented. A state-of-the-art embedded digital controller was deployed on Linux leveraging design re-use, implementation portability, scalability as well as designer flexibility. To tackle the performance limitations, to increase system determinism and the overall latency time of the controller, the operating system overhead was minimized by (1) offloading critical software components of the controller to FPGA, (2) minimizing user- and kernel-space memory crossings to a minimum, and (3) exploring FPGA-based platforms and their communication interfaces, to promote high speed control and communication concurrency.

Multithreading is a key feature for dealing with the complexity of current generation embedded devices. Real-Time Operating Systems (RTOSes) provide a higher level of abstraction that alleviates design complexity and time-to-market pressure, inducing, however, undesired latencies and unpredictable execution times. Research works have been focusing on improving performance, determinism or agnosticism, but none simultaneously tackled the three metrics. This work in progress paper presents RT-SHADOWS, a co-designed architecture that promotes configurability, determinism and agnosticism from the outset. A multi-thread ARM softcore processor was exploited and extended by offloading the scheduling-related features into the hardware layer. The hardware multi-thread support is transparent for the standard RTOS applications and independent of the Operating System (OS). Promising preliminary results demonstrate huge improvements on performance and determinism, with only a small cost on hardware.

With the growing ubiquity of Internet of Things (IoT), myriads of smart devices connect and share important information over the Internet. In order to provide connectivity and interoperability of all the existing heterogeneous wireless devices, a full communication stack is proposed by the IoT Architecture Reference Model (IoT-ARM). From the sensor to the cloud, the proposed stack can be implemented on all IoT devices avoiding the battle for the wireless standard that will be adopted. This work in progress paper proposes an FPGA-based edge device for IoT, which uses SoC (System-on-Chip) FPGA technology to offload critical features of the communication stack to dedicated hardware, aiming to increase systems performance.

The pervasive use of embedded computing systems in modern societies altogether with the industry trend towards consolidating workloads, openness and interconnectedness, have raised security, safety, and real-time concerns. Virtualization has been used as an enabler for safety and security, but research works have proven that it must be extended and improved with hardware-based security foundations. ARM Trustzone has been used for the realization of Trusted Environments, however in this case real-time requirements are completely disregarded. This work in progress paper presents FreeTEE, an embedded architecture that emphasizes and preserves the real-time properties of the system but still guarantees security from the outset. TrustZone technology is exploited to implement the basic building blocks of a Trusted Execution Environment (TEE) as a lower-priority thread of a RTOS. Preliminary results demonstrated that the real-time properties of the RTOS remain practically intact.

Migration to multicore is inevitable. To harness the potential of this technology, embedded system designers need to have available operating systems (OSes) with built-in capabilities for multicore hardware. When designed to meet real-time requirements, multicore SMP (Symmetric Multiprocessing) OSes not only face the inherent problem of concurrent access to shared kernel resources, but still suffer from a bifid priority space, dictated by the co-existence of threads and interrupts. This work in progress paper presents the offloading of the FreeRTOS kernel components to a commercial-off-the-shelf (COTS) multicore hardware. The ARM Generic Interrupt Controller (GIC) is exploited to implement a multicore hardware-centric version of the FreeRTOS that not only solves the priority inversion problem, but also removes the need of internal software synchronization points. Promising preliminary results on performance and determinism are presented, and the research roadmap is discussed.

Virtualization has been used as the de facto technology to allow multiple operating systems (virtual machines) to run on top of the same hardware platform. In the embedded systems domain, virtualization research has focused on the coexistence of real-time requirements with non-real-time characteristics. However, existent standard software-based virtualization solutions have been shown to negatively impact the overall system, especially in performance, memory footprint and determinism. This work in progress paper presents the implementation of an embedded virtualization architecture through commodity hardware. ARM TrustZone technology is exploited to implement a lightweight virtualization solution with low overhead and high determinism, corroborated by promising preliminary results. Research roadmap is also pointed and discussed.

Wireless Sensor Networks are an emerging technology which has been recently adopted in many applications. Due to its wireless nature, the analysis of the radio propagation models plays an important role for performance evaluation in both theoretical and practical aspects. In this regards, path loss exponent is one of the most important parameter which has been considered widely in wireless communications analysis. There are several theoretical evaluations of path loss exponent for wireless sensor networks available in the literature. However there is a lack of experimental evaluation of both path loss exponent and the effect of shadowing. In this paper, three environments (free space, in building and industrial), where wireless sensor nodes are widely deployed, have been chosen in order to evaluate the experimental analysis. Path loss and path loss exponent are measured by means of Received Signal Strength Indicator (RSSI) and based on them, the standard deviation of shadowing effect is also calculated. All the measured parameters are compared with the theoretical analysis available in the literatures.

Due to the scientific and technological advances of the last decades, embedded systems have become central to modern life, which has led to a new reality in which the embedded systems market has been growing with a monthly or even weekly emergence of new products with different applications across several domains. Focus on embedded systems design is driven by: (1) high and fast penetration in products and services due to the integration of networks, operating systems and database capabilities, (2) the economically strategic nature of the field, and (3) its status as a new, and relatively undefined, subject in academic environment. We'll present the development of the educational context for the new technologies, and show how our Integrated Master Curriculum in Industrial Electronics and Computer Engineering has been adapted to satisfy the needs of the industry and meet all the above mentioned challenges.

This paper describes an agile model-driven generative software development paradigm supported by mainstream tools to offer a significant leverage in hiding commonalities and configuring variabilities across families of video surveillance products while maintaining the new product quality. The integration of Agile and SPL (Software Product Line) paradigms is promoted to develop video surveillance systems as a pay-as-you-go fashion rather than developing an ex-nihilo new product, despite the perceived incompatibilities of these paradigms and potential challenges of such integration.

The development and maintenance of hardware/software Systems with a high level of variability is a complex task. At IVV Automacão, LDA the video surveillance system is implemented as a software product line that exploit the common component features that compose the video surveillance system family of products. In order to manage the system variability at code level, the IVV developers use C++ template metaprogramming (TMP). Although, TMP presents advantages in variability code management at compile time, the syntax and idioms of TMP are esoteric compared to conventional C++ programming, and TMP can be difficult to understand. In this paper we propose a novel approach to implement and maintain TMP code using a model-driven tool, that employs Template Markup Language with a XSLT transformer to automatic generate and maintain TMP code.

This paper presents a novel hypervisor engineered for aerospace applications using an object oriented approach embodying time and space partitioning (TSP) on a PowerPC core embedded in a FPGA, for the NetworkCentric core avionics [1] - an architecture of cooperating components and managed by a real-time operating system to implement dependable computing and targeting simplicity. To support partitioned IMA [2]software architectures our hypervisor adapted to the aerospace application domain the Popek and Goldberg's [3] fidelity, efficiency and resource control virtualization requirements by extending them with additional ones like timing determinism, reactivity and improved dependability. A distinctive feature of the hypervisor is its I/O device virtualization approach that guarantees real-time performance and small trusted computing base.

The heterogeneity of device interfaces and the disparity between interconnection standards leads to difficulty in achieving seamless device interoperability. The Open Services Gateway Initiative (OSGi) framework attempts to provide a unified Residential Service gateway by abstracting from the device interface and providing transparent methods for Service Oriented Architectures. However, it is not yet compliant with all standards and unsuited for some. This paper presents the development of a Multi-Camera Home Network System, using devices which implement three different protocols. The OSGi gateway bundles to handle the interoperability are described including one OSGi bundle for ONVIF devices. A Residential Service OSGi gateway is also presented and the difficulties faced with the integration of video streaming on the framework are presented, as well as the solutions used to tackle the problem.

This paper presents a novel segmentation approach for object detection in aquatic outdoor scenes such as swimming pools and its surroundings. This process is part of a video-based early drowning detection system for private swimming pools. Aquatic outdoor scenes are continuously changing due to reflections and refractions caused by water oscillation, severely affecting the results obtained by traditional segmentation schemes because water oscillation is perceived as motion detection of objects in the aquatic area. The novel segmentation technique is based in the separation of the special water environment and the rest of the scene, by means of an off-line automatically generated pool mask. The two areas are segmented with different algorithms, one for the aquatic scene and another for the surrounding area. Further, a two-step approach segmentation algorithm for the aquatic area was developed: the first segmentation step is based on the HSV invariant color model space; the second one consists in re-segmenting each region inside an expanded bounding box resulting from the first step. The second step increases segmentation quality up to 20%, as it captures parts of objects not detected before. The information extracted from the water surrounding area is also very important for object tracking and behaviour analysis purposes.

In this paper a real-time control system, developed to control a single-phase shunt active power filter used to minimize problems related to power quality in electrical systems is presented. The power stage of the active filter is based on a one-leg inverter, with two capacitors in the dc side, and a filter inductor in the ac side. The control system is based on the instantaneous power theory in the α-β-0 reference frame (pq-theory), modified to be applied in single-phase systems. In essence, the shunt active filter is designed to drain, from the electric grid, harmonic and reactive components of the load currents, such that the source current will become an almost sinusoidal waveform, with low harmonic distortion, and in phase with the system voltage. The control system is implemented using a development board (Atmel NGW100) and ensures simultaneous real-time acquisition of voltage and current data, the proposed system is capable of acquiring eight analog channels (16-bit resolution) simultaneously at 150ksps, based in the acquire data the power components calculation and compensation is performed accordingly to the p-q theory.

Frameworks are a fundamental reuse technique, but they are often hard to learn and reuse. Documentation approaches and tools supporting instantiation have been the main research subjects for addressing framework reuse difficulties. This paper introduces a new approach that starts from a more fundamental level - framework characteristics. These are shaped by programming and design techniques, and their impact on reuse difficulties is analysed. From there, a framework model making a congruent combination of characteristics is defined. The results are demonstrated with a case study framework. Both the problem analysis and the proposed solution are relevant for the conference topics, namely framework reuse and design methods.