A simulation tool-box and its applications to computer-aided design and scaling of deep-submicron CMOS are presented. The simulation tools are grouped around a mixed level approach and cover a wide range of applications. Due to the mixed-level approach, fast table models and accurate numerical models can be combined simultaneously in a single circuit simulation. Device and circuit characteristics can be accurately represented as functions of technical parameters, even in the deep-submicron region. The application of the toolbox is demonstrated for some examples from the fields of device design and SRAM scaling. The gate-drain overlap and junction depth of 0.4- mu m devices are optimized with respect to circuit performance and device degradation. Different drain structures and supply voltages for 0.25- mu m devices are compared. Scaling of CMOS SRAM's from 0.7 to 0.4 mu m and finally to 0.25- mu m gate length is simulated. The relevance of device structure, design rules, and supply voltage for speed, power dissipation, and chip area are pointed out and their influence on circuit performance predicted.>

Signal delay, chip area, and power dissipation are conflicting criteria for designing high-performance VLSI MOS circuits. Global optimization of transistor sizes in digital CMOS logic circuits with the design tool multiobjective gate-level optimization (MOGLO) is described. Analytical models for the design objectives are presented, and algorithms are discussed. Different techniques were combined to solve the circuit optimization problem with low computational costs. Precise gate-level delay models guarantee meaningful results, especially for high-speed logic circuits.>