This paper presents a comprehensive analysis of the impact of a generic power amplifier’s (PA’s) output power on the bit-error-rate (BER) in a transceiver employing a 4Mquadrature amplitude modulation (QAM) scheme. The study highlights the dual effects of excessive and insufficient output power on system performance. On one hand, low output power reduces the signal-to-noise ratio (SNR) at the receiver, leading to increased BER. On the other hand, high output power pushes the PA into its nonlinear region, similarly degrading BER. A quantitative analysis is conducted to examine the combined influence of noise and nonlinearity on BER. From this analysis, the globally optimal PA output power that minimizes BER for a wireless system is derived. Theoretical insights are validated through system-level simulations, demonstrating the effectiveness and high accuracy of analytical expressions.

The new philosophy of realizing high-order modulation schemes directly in the RF domain enables the generation of spectrally efficient$4^{M}$quadrature-amplitude-modulated$(4^{M}$QAM) symbols using the vectorial summation of$M$quadrature phase-shift keying (QPSK) signals. As will be shown in this paper, this approach, called RF-QAM, leads to several remarkable advantages in power amplification and signal formation in terms of both performance and power consumption. This paper presents a study of the RF-QAM transmitter (TX) and a comparison with the conventional architecture, as well as analytical studies and simulations to verify the superior performance of the RF-QAM transmitter compared to the conventional counterpart.

Realization of high-order modulation schemes directly in the RF domain enables the generation of spectrally efficient$4^M$quadrature-amplitude-modulated ($4^M$QAM) symbols using the vectorial summation of$M$quadrature phase-shift keying (QPSK) signals whose amplitudes are progressively scaled by a constant factor of two. Called RF-QAM, this approach leads to numerous advantages including the elimination of power-hungry digital-to-analog converter (DAC) and the mitigation of stringent linearity requirement of the front-end power amplifier (PA). This paper presents a comprehensive comparative study of RF-QAM and conventional transmitters. The design issues associated with the front end and the mixed-signal blocks for both architectures are investigated, and the performance of these two designs is compared. Various circuit-and system-level simulations verify the superior performance of the RF-QAM transmitter compared to the conventional counterpart.

This article presents a current-adjusting auto-zeroing (CAAZ) scheme that overcomes the critical shortcomings of state-of-the-art auto-zero-based offset and low-frequency noise cancellation methods. The proposed technique appropriately adjusts the bias current of individual branches within the amplifier to cancel dc offset and low-frequency noise. The CAAZ method does not suffer from thermal-noise increase due to input signal division and stability issues encountered in input auto-zero (IAZ) or limited allowable gain and input swing experienced in the output auto-zero (OAZ) method. Moreover, it does not create any feedback loop during its operation phases and, thus, does not impose additional stability restrictions on the amplifier within which it is being used. Two differential amplifiers, a single-stage differential amplifier (SSDA) and a folded-cascode amplifier (FCA), employing the proposed CAAZ technique, are designed and simulated in a standard 180-nm CMOS process. Simulation results verify the higher performance of the proposed CAAZ compared to the conventional counterparts.

A phase-locked-based frequency synthesizer – ubiquitously used to generate local oscillation in a communication transceiver – exhibits phase noise and jitter which considerably degrades bit-error rate (BER) and error vector magnitude (EVM) of a digital communication link. This paper presents an analytical study of EVM and BER degradation for a variety of widely used digital modulation schemes. Phase noise and jitter of a generic integer-N phase-locked loop (PLL) as a local oscillator feeding an RF mixer are derived, while accounting for the reference spurs and cyclo-stationarity of the mixer operation as well as the additive noise of the communication link. This jitter model is then utilized to directly study its impact on digital modulation constellations. Specifically, the EVM and BER degradation due to the PLL jitter in communication systems incorporating M-ary phase-shift keying (M-PSK) and${4^{M}}$quadrature amplitude modulation (${4^{M}}$QAM) are analyzed. Comparison between analytical models and system-level simulations verifies an excellent accuracy of these models.

This paper presents an analytical model for calculating the output voltage and the power efficiency of multi-stage multi-output (MSMO) DC-DC converters (DDC) that use charge pump cells for boosting the voltage. Various cases such as multi-output current consumption and its effects on the output voltage and the power efficiency are studied. Based on the model, a tapered design approach is proposed that can bolster the power efficiency and lower the output voltage drop of MSMO DDCs. Moreover, a charge-pump-based DDC is introduced and designed to verify the proposed model. Simulation results using a standard high-voltage 180-nm CMOS technology affirms the accuracy of the presented model.

An analysis of noise in passive sampling mixers is presented, which is based on derivations of auto- and cross- correlation functions that capture statistical co-dependence of noise components during the tracking and hold phases of sampling mixer operation. This study accurately predicts the noise-folding due to cyclostationarity of the sampling noise of the mixer. As will be discussed, notwithstanding its simple form, the proposed approach yields an accurate noise model, which will simplify to existing noise models presented by prior work under their adopted assumptions.

A 53-61GHz low-power charge-pump PLL is presented. This integer-N type-II PLL employs a class-D V-band VCO and a divide-by-1024 chain. The first divider in the chain is an inductor-less divide-by-4 injection-locked frequency divider (ILFD). The proposed PLL is fabricated in a standard 65nm CMOS process. The VCO employs a harmonic positive feedback technique to boost the fundamental signal swing, which leads to better phase noise performance at low supply voltage and DC power consumption compared to prior work. The VCO consumes the minimum power of 10.6mW from 0.8V supply. The PLL achieves a wide tuning range of 13% from 53.35- to 60.83-GHz and a phase noise of -88 dBc/Hz at 1MHz offset, while consuming a minimum DC power of 48mW. This PLL can be used as part of the LO generation network for millimeter-wave phased-array transceivers.

The emergence of Internet of Things (IoT) has brought forth new opportunities by seamlessly integrating the physical world using computing, sensing, and wireless networks, transforming it into a cyber-physical system. An essential building block enabling an IoT is a sensing system. The use of "near-field communication (NFC)" has gained attention in recent years, as it enables low-power short-range sensing and wireless transfer of low content information. The NFC, however, is inapplicable in scenarios where the real-time high-resolution image or video of the object(s) needs to be sensed. The penetration of THz waves through many materials, which are impervious for visible light makes THz imaging akin to X-rays, except that THz radiation is non-ionizing and therefore not harmful to the object being imaged, especially living tissues. This special issue paper presents an overview of recent advances in the development of siliconbased mm-wave/THz imaging sensors for near-field IoT applications.

This paper improves the performance of the polar quantizer for wireless signals with complex Gaussian probability density functions (PDFs) first proposed by Nazari et al. A new signal-to-quantization noise ratio (SQNR) enhancement technique based on magnitude segmentation of polar space is employed, which can boost the SQNR of the quantizer significantly compared to that of the conventional rectangular and polar quantizers. First, an N-segmentation technique is examined using N different bit allocations for magnitude and phase quantizers. The study then covers a polar quantizer incorporating a three-segmentation technique for practical implementation. Using this technique, the overall maximum SQNR of the polar quantizer improves about 2.5 dB higher than the rectangular quantizer. In addition, over 14 dB SQNR improvement at low average magnitude is achieved if equal numbers of quantization levels for both polar and rectangular quantizers are utilized.

This paper presents design and implementation of a 12-GS/s fully differential data acquisition (DAQ) system-on-chip (SoC) fabricated in a standard 130-nm CMOS process. The proposed DAQ is comprised of a 4-bit flash ADC and four channels of 1:32 demultiplexer (DEMUX) with on-chip custom registers. At 12-GS/s sampling rate, the DAQ SoC achieves an SNDR of 19.2 dB for 2.9-GHz input signal and 24.2 dB for low-frequency inputs. The flash ADC and each DEMUX channel consume 200- and 260-mA from 1.3 V supply and occupy an active area of 0.85 and 0.70${\mathrm{ mm}}^{2}$, respectively. The DAQ SoC does not employ time interleaving and calibration techniques. In the meantime, no BW- or speed-enhancing inductors have been used in the proposed system. The DAQ prototype achieves the highest sampling rate in 130-nm CMOS technology.

Recent studies show that peripheral circuit (including decoders, wordline drivers, input and output drivers) constitutes a large portion of the cache leakage. In addition, as technology migrates to smaller geometries, leakage contribution to total power consumption increases faster than dynamic power, indicating that leakage will be a major contributor to overall power consumption. This paper presents zig-zag share, a circuit technique to reduce leakage in SRAM peripherals by putting them into low-leakage power sleep mode. The zig-zag share circuit is further extended to enable multiple sleep modes for cache peripherals. Each mode represents a trade-off between leakage reduction and the wakeup delay. Using architectural control of multiple sleep modes, an integrated technique called MSleep-Share is proposed and applied in L1 and L2 caches. MSleep-share relies on cache miss information to guide leakage control mechanism and switch peripheral circuit's power mode. The results show leakage reduction by up to 40× in deeply pipelined SRAM peripheral circuits, with small area overhead and small additional delay. This noticeable leakage reduction translates to up to 85% overall leakage reduction in on-chip memories.

A CMOS current-reuse transmitter for ultra-low power (ULP) applications is presented. It can provide up to 10.2dBm of output power with a total efficiency of 30% at 2.4GHz. By utilizing the stacking technique, the average current of a class-E power amplifier is reused by the accompanying VCO and an optional RX block. The breakdown issue associated with the class-E PA is mitigated. A detailed analysis of the current-reuse structure is demonstrated. Practical design issues are discussed and appropriate design guidelines are provided.

Conventional multi-antenna receiver front-ends require multiple RF/baseband chains and analog-to-digital converters (ADC). This increases power consumption and chip area substantially. In this letter, we introduce a new Code-Modulated Path-Sharing Multi-Antenna (CPMA) receiver architecture suitable for any multi-antenna scheme including spatial multiplexing, spatial diversity, and beamforming. The receiver uses code modulation to distinguish the antenna signals before combining them in the analog domain. The combined signal propagates through shared-path blocks and all the original signals are later recovered in the digital domain for further processing. Due to the spread spectrum nature of code modulation, a larger bandwidth is needed for the blocks in the shared path. To alleviate this effect, the use of non-orthogonal coding is examined. An effective channel matrix is derived and the system capacity is evaluated in terms of the cross-correlation between signature codes. Implementation and code selection issues are discussed. Analysis and simulation results indicate that by properly selecting non-orthogonal code sets, the spreading factor, and therefore, the overall analog signal bandwidth is reduced while incurring minimal performance degradation.

Conventional multi-antenna systems require multiple RF chains, baseband blocks, and analog-to-digital converters (ADC) in the receiver front-end, mandating substantial increases in power consumption and chip area. In this paper, we introduce a new universal code-modulated path-sharing multi-antenna (CPMA) receiver architecture suitable for any multi-antenna scheme including spatial multiplexing and spatial diversity. The receiver utilizes code modulation to distinguish different antenna signals before combining them in the analog domain. The combined signals propagate through a single shared path and are later recovered in the digital domain for further processing. Due to the spread spectrum nature of code modulation, a larger bandwidth is required for the blocks in the shared path. To alleviate this effect, we examine the use of non-orthogonal signature codes. Analysis and simulation results indicate that by properly selecting non-orthogonal code sets, the spreading factor, and therefore, the overall analog signal bandwidth is reduced while incurring minimal performance degradation.

In the presence of high-power environmental noise, such as that present in the common substrate and on the power and ground (P/G) rails of a system-on-a-chip (SOC), the current-to-phase relationship for an LC oscillator cannot be assumed linear. This paper presents a simple nonlinear modification to the well-established linear time-variant (LTV) model for phase noise that facilitates a more accurate prediction of oscillator phase noise and jitter in the presence of high-power noise. For low-power noise, this nonlinear model simplifies to the LTV metric. The accuracy of the proposed analytical model is verified through the simulation of a 10 GHz Colpitts oscillator in a 0.18μm CMOS process.

This paper presents a novel LC oscillator, capable of operating at frequencies beyond 100 GHz in a standard 0.13 mum CMOS process. A new phase noise reduction technique using higher order LC filter is introduced and theories are discussed. Custom designed coplanar waveguides from 3D electromagnetic simulation are employed, and a corresponding circuit model is extracted from an S-parameter optimization technique

This paper presents a novel power optimization technique for ultra-low power (ULP) RFICs. A new figure of merit, namely the gmfT-to-current ratio, (gmfT/ID), is defined for a MOS transistor, which accounts for both the unity-gain frequency and current consumption. It is demonstrated both analytically and experimentally that the gmfT/ID reaches its maximum value in moderate inversion region. Next, using the proposed method, a power optimized common-gate low-noise amplifier (LNA) with active load has been designed and fabricated in a CMOS 0.18μm process operating at 950MHz. Measurement results show a noise-figure (NF) of 4.9dB and a small signal gain of 15.6dB with a record-breaking power dissipation of only 100μW.

The paper studies low-power ultra wideband (UWB) transceiver architectures. First, three different architectures for the impulse-radio UWB transceiver are studied, while investigating the power-performance tradeoffs. The paper illustrates that a more power-efficient architecture should perform part of the signal processing in the analog-domain. Next, the multiband UWB transceiver is studied and power-efficient circuits for the front-end of the UWB transceiver are presented. Finally, the performance and power consumption of these transceivers are compared and a number of design indications are provided.

Rapid technology scaling along with the continuous increase in the operation frequency cause the crosstalk noise to become a major source of performance degradation in high-speed integrated circuits. This paper presents an efficient metric to estimate the capacitive crosstalk in nanometer high-speed very large scale integration circuits. In particular, we provide closed-form expressions for the peak amplitude, the pulsewidth, and the time-domain waveform of the crosstalk noise. Experimental results show that the maximum error of our noise predictions is less than 13%, while the average error is only 5.82%.

This paper presents the design and analysis of a novel distributed CMOS mixer for ultrawide-band (UWB) receivers. To achieve the UWB RF frequency range required for the UWB communications, the proposed mixer incorporates artificial inductance-capacitance (LC) delay lines in radio frequency (RF), local oscillator (LO), and intermediate frequency signal paths, and single-balanced mixer cells that are distributed along these LC circuits. Closed-form analytical model for the conversion gain of the mixer is presented. Furthermore, a comprehensive noise analysis of the proposed distributed mixer is carried out, which includes calculation of the mixer noise figure (NF) and derivation of the optimum number of stages, n, minimizing the NF. The designed mixer is capable of covering the RF and LO frequencies over a wide range of frequencies from 3.1-8.72 GHz. A two-stage distributed mixer has been fabricated in a 0.18-/spl mu/m CMOS process. Experiments show a conversion gain of more than 2.5 dB for the entire range of the frequencies. The dc power consumption is 10.4 mW.

A comprehensive study of ultrahigh-speed current-mode logic (CML) buffers along with the design of novel regenerative CML latches will be illustrated. First, a new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, two new high-speed regenerative latch circuits capable of operating at ultrahigh-speed data rates will be introduced. Experimental results show a higher performance for the new latch architectures compared to the conventional CML latch circuit at ultrahigh-frequencies. It is also shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.

This paper investigates the impact of clock jitter induced by substrate noise on the performance of the oversampling DS modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the clock jitter in clock generators incorporating phase-locked loops (PLLs). Next, the effect of the clock jitter on the performance of the DS modulator is studied. It will be shown that substrate noise degrades the signal-to-noise ratio of the DS modulator while the noise shaping does not have any effect on clock jitter induced by substrate noise. To verify the analysis experimentally, a circuit consisting of a second-order DS modulator, a charge-pump PLL, and forty multistage digital tapered inverters driving 1pF capacitors is designed in a 0.25mm standard CMOS process. Several experiments on the designed circuit demonstrate the high accuracy of the proposed analytical models.

A current-mode logic (CML) buffer is based on a simple differential circuit. This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a chain of tapered CML buffers is proposed. The circuit design issues in regard to the CML buffer are compared with those in a conventional CMOS inverter. It is shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.

This paper presents the design of a high efficiency, low THD, 5.7GHz fully differential power amplifier for wireless communications in a standard 0.18mm CMOS technology. The power amplifier employs a fully differential class-E topology to achieve high power efficiency by exploiting its soft-switching property. In order to achieve high operating frequency, an injection-locked oscillator is utilized, which makes the output voltage of the power amplifier tuned at the input signal frequency. A complementary CMOS cross-coupled pair topology is employed to realize the LC-tank oscillator because it has lower phase-noise, thereby giving lower THD than the single NMOS cross-coupled pair topology. The proposed power amplifier can deliver 25dBm output power to a 50Ω load at 5.7GHz with 42.6% power-added efficiency (PAE) from 1.8V supply voltage.

This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.

This paper presents a numerically stable and efficient algorithm for model reduction of large RLC networks using frequency-weighted balanced truncation technique. The salient features of this algorithm include guaranteed stability of the reduced transfer function as well as availability of provable frequency-weighted error bounds. Such frequency weighting is essential to provide better control over time-domain error of the reduced system. The first k largest singular values of the system are obtained using the Lanczos algorithm, and the Lyapunov equations are solved by an iterative Lyapunov equation solver. Experimental results demonstrate the higher accuracy of our technique compared to Krylov-subspace-based model reduction techniques and other truncated balanced realizations that do not use spectral shaping. Based on MATLAB simulations, the run-time of our method is only 5% more than that of PRIMA.

This paper presents a spectrally-weighted balanced truncation technique for RLC interconnects, a technique needed when the interconnect circuit parameters change as a result of variations in the manufacturing process. The salient features of this algorithm are the inclusion of parameter variations in the RLC interconnect, the guaranteed stability of the reduced transfer function, and the availability of provable frequency-weighted error bounds for the reduced-order system. This paper shows that the balanced truncation technique is an effective model-order reduction technique when variations in the circuit parameters are taken into consideration. Experimental results show that the new variational spectrally-weighted balanced truncation attains, on average, 20% more accuracy than the variational Krylov-subspace-based model-order reduction techniques while the run-time is also, on average, 5% faster.

Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2 GHz has caused crosstalk noise to become a serious problem, that degrades the performance and reliability of high speed integrated circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI circuits. In particular, we provide closed-form expressions for the peak amplitude, the pulse width, and the time-domain waveform of the crosstalk noise. Experiments show that our analytical predictions are at least two times better than the previous models in terms of the prediction accuracy. More precisely, experimental results show that the maximum error of our predictions is less than 10% while the average error is only 4%. Finally, based on the proposed analytical models, we discuss the effects of transistor sizing and buffering on crosstalk noise reduction in VLSI circuits.

CMOS phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper, a general comprehensive stochastic model of the power/ground (P/G) noise in VLSI circuits is presented. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise. The PLL timing jitter is predicted in response to the VCO phase noise. Next, the design of a low power, 2.5 V, 0.25 /spl mu/ CMOS PLL clock generator with a lock range of 100 MHz-400 MHz is described. Our mathematical method is utilized to study the jitter-induced P/G noise in this PLL. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.

This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the buffer propagation delay and the optimum taper factor is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. The effect of the on-chip decoupling capacitor on ground bounce waveform and the circuit performance is analyzed next and a closed form expression for the peak value of the differential mode component of the ground bounce in terms of on-chip decoupling capacitor is provided. Finally a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.

In this paper, we present a new analytical approach for computing the ramp response of an RLC interconnect line with a pure capacitive load. The approach is based on the two-port representation of the transmission line and accounts for the output resistance of the driver and the line inductance. The results of our analysis are compared with the results of HSPICE simulations demonstrating the high accuracy of our solution under various values of driver, interconnect, and load impedances.