Currently available very large-scale integrations (VLSIs) are vulnerable to radiation, as measured in terms of soft error and total-ionizing-dose. Therefore, by following a repairable VLSI concept, we have been developing a radiation-hardened optical reconfigurable gate array VLSI that can support a use of a partially damaged VLSI. Earlier development efforts have fabricated a 1 Grad total-ionizing-dose tolerant radiation-hardened optical reconfigurable gate array VLSI using the repairable VLSI concept. However, since stabilized power supply units are also vulnerable to radiation, a radiation-hardened optical reconfigurable gate array VLSI with no stabilized function must be used with a battery in intense radiation environments such as the Fukushima Daiichi Nuclear Power Plant. This paper presents the operating voltage range of a radiation-hardened optically reconfigurable gate array VLSI. These findings confirm that a battery direct drive is possible for a radiation-hardened optically reconfigurable gate array VLSI.

Radiation-hardened very large scale integrations (VLSIs) have become widely necessary for use in space systems, radiation medicine, high-energy physics research, nuclear power plants, decommissioning operations at nuclear power plants, and for the designs of future nuclear fusion reactors. Nevertheless, conventional radiation-hardened VLSIs have retained extreme vulnerability to radiation, with total-ionizing-dose (TID) tolerances limited to 1–20 kGy. Therefore, this paper presents a proposal to increase the TID toler-ance of a radiation-hardened field programmable gate array (FPGA) using a triple-modular redundant configuration function driven by a two-phase non-overlapping clock. Experiment results show that the FPGA has achieved a TID tolerance of 7.3 MGy, which is 365-7,300 times higher than that of existing radiation-hardened VLSIs.

This paper presents the total-ionizing-dose tolerance evaluation of an optoelectronic field programmable gate array (FPGA) during operation. The optoelectronic FPGA was fabricated using 0.18${\mu m}$standard complementary metal oxide semiconductor (CMOS) process technology. An experiment assessing the total-ionizing-dose tolerance of the optoelectronic FPGA was conducted at a 2.27–2.28 kGy/h dose rate using a60Co gamma radiation source. Results clarified that the optoelectronic FPGA can function correctly under a 2.27–2.28 kGy/h dose rate and that the total-ionizing-dose tolerance of the optoelectronic FPGA is greater than 80 Mrad during operation. The total-ionizing-dose tolerance result is 80 times higher than that of typical radiation-hardened very large scale integrated circuits (VLSIs) and typical radiation-hardened FPGAs.

This paper presents a proposal for a sequential circuit implementation method for multi-context scrubbing operations that can treat soft-error and permanent failure issues simultaneously. Although multi-context scrubbing operations can treat permanent failure issues on field programmable gate arrays (FPGAs), implementing sequential circuits is difficult because the flip-flop location must be changed while maintaining sequential operations. Therefore, no multi-context scrubbing operation including a sequential circuit has been demonstrated to date. As described herein, a multi-context scrubbing operation using a simple 8-bit counter circuit has been demonstrated perfectly on an Artix-7 FPGA (XC7A35TICSG324-1L). This paper presents experimentally obtained results of that demonstration.

Robot control operation is always implemented onto a processor-based embedded system. However, if a robot operation was implemented onto an FPGA as hardware operation, the robot operation could be accelerated. Since currently high-level synthesis tool is available, a C++ designed operation can easily be translated onto the corresponding FPGA hardware. In this paper, we present the hardware implementation of control algorithm of a robot with 6 legs on an Arria10 SOC field programmable gate array using Cyber Work Bench as a high-level synthesis tool.

Recently, radiation-hardened SRAM-based field programmable gate arrays (FPGAs) and radiation-hardened flash-based FPGAs have been used frequently for space systems. The total-ionizing-dose tolerances of such radiation-hardened FPGAs are limited to a 1 Mrad total-ionizing-dose. Therefore, space embedded systems must be surrounded by heavy shielding material. However, if a shield-less space embedded system could be achieved, then rocket launch costs could be decreased. This paper therefore presents a proposal of a new radiation-hardened optically reconfigured gate array exploiting its parallel configuration. The total-ionizing-dose tolerance of the radiation-hardened optically reconfiguration gate array has been measured experimentally as a 406 Mrad total-ionizing-dose using a cobalt 60 gamma radiation source, demonstrating at least 406 times higher radiation tolerance than those of currently available radiation-hardened FPGAs.

For research related to field programmable gate arrays (FPGAs), various FPGA game solvers have been developed recently. The FPGA game solver can achieve up to 1,000 times faster processing speeds than processor-based operations. This paper presents one development of such FPGA game solvers: an FPGA Trax Solver based on a neural network design. The speed of the FPGA Trax Solver operations implemented on an FPGA (Arria II GX; Altera Corp.) is over 60 times greater than operation of C++ based software on a personal computer (Vostro 460; Dell Inc.).

Optically reconfigurable gate arrays (ORGAs) have been developed to achieve a high-performance FPGA with numerous configuration contexts. In the architecture, an optical memory technology or a holographic memory technology has been introduced so that the architecture can have numerous configuration contexts and high-speed reconfiguration capability. Results show that the architecture can achieve a large virtual gate count that is much larger than those of currently available VLSIs. To date, ORGAs with a spatially multiplex holographic memory have been reported. However, the spatially multiplexed holographic memory can only have a small number of configuration contexts, which are limited to about 256 configuration contexts. To implement more than a million configuration contexts, an angle-multiplex holographic memory must be used. However, no ORGA with an angle multiplex holographic memory that can sufficiently exploit the huge storage capacity of a holographic memory has ever been reported. Therefore, this paper presents a proposal of a novel ORGA with an angle-multiplexed holographic memory. The architecture can open the possibility of providing a million configuration contexts for a multi-context FPGA.

Recently, several varieties of image recognition systems using Fourier transform have been proposed. The salient benefit of using a Fourier transform is its position-independent image recognition capability. However, the operation of Fourier transform of high-resolution images is an extremely heavy operation. This paper therefore presents a proposal of image recognition systems using an optical Fourier transform on a dynamically reconfigurable vision architecture. This proposed system can recognize numerous images within an extremely short period using dynamic reconfiguration.

Recently, for use in autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. However, to recognize numerous images quickly, such systems require many template images to be read out dynamically from memory. They must then be sent to a processor quickly. Achieving such high-speed real-time image recognition operation is difficult because of the bottleneck of the transfer between the memory and the processor. To alleviate that bottleneck, a dynamically reconfigurable vision architecture was proposed. This paper presents 16-gray scale image recognition operation of the proposed architecture.

This paper presents a proposal of a color configuration method for an optically reconfigurable gate array (ORGA). A conventional ORGA consists of a single-wavelength laser array to address configuration contexts. However, the new ORGA has lasers of some other wavelength inside a laser array. Consequently, the addressable number of configuration contexts can be increased.

Recently, many game programs have been developed aggressively as hardware on field programmable gate arrays (FPGAs) because of the extremely large solution space of such games as the Connect6 game, Blokus Duo game, and others so that the computational capabilities of computers are currently insufficient to search all possible solutions. This report describes an FPGA acceleration experiment for the Blokus Duo game. The FPGA Blokus Duo Solver was implemented on an Arria II GX FPGA (Altera Corp.). Its operation speed is 25 times faster than C++ based software operation of the same algorithm on a Core i7 processor.

Currently, demand for high-speed dynamic reconfiguration of a programmable device is increasing for raising the performance level of such devices. To support high-speed dynamic reconfiguration, optically reconfigurable gate arrays (ORGAs) have been developed to date. An ORGA consists of a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. The holographic memory can store many configuration contexts. Moreover, its large-bandwidth optical connection enables high-speed reconfiguration. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-gate-count ORGA-VLSIs. Therefore, a 0.18 μιη CMOS process photodiode memory has been newly fabricated to increase the gate density of ORGAs. The photodiode memory uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory.

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array. An ORGA's programmable gate array with more than 100 reconfiguration contexts can be reconfigured in nanosecond-order. In addition to that beneficial feature, ORGAs can be reconfigured with invalid configuration data that have been damaged by high-energy charged particles in a radiation-rich space environment. Even if 35 % or 5,915 pixels of holographic memory data are damaged by high-energy charged particles, the ORGA can execute configuration operations correctly. Therefore, ORGAs are sufficiently robust devices for use in space-radiation environments. This paper presents a proposal of a more advanced dependability-increasing technique on a multi-context ORGA. This technique can raise the ORGA's level of configuration dependability even further by exploiting multi-context implementation.

Demand is increasing daily for a robust VLSI chip that is useful in a radiation-rich environment. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a radiation-tolerant Field Programmable Gate Array (FPGA). The ORGA architecture is extremely robust against multi-event upsets. Moreover, it can recover from permanent errors resulting from a heavy total radiation dose. This paper presents demonstration results of a 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed-adjustment function.

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array. An ORGA's programmable gate array can be reconfigured at nanosecond-order, with more than 100 reconfiguration contexts. In addition to that beneficial feature, since ORGAs can be reconfigured with invalid configuration data that have been damaged by high-energy charged particles in a radiation-rich space environment, ORGAs are suitable for space applications. The robust capability of ORGAs with an amplitude modulation type holographic memory has already been demonstrated, but an ORGA with a phase-modulation type holographic memory that can achieve more robust capability has never been reported. Therefore, this paper presents a proposal of a new dependable ORGA architecture based on a phase-modulation type of holographic memory. In addition, this paper describes experimental clarification through a demonstration that the dependable ORGA is more robust than conventional ORGAs with an amplitude modulation type holographic memory.

Recently, immediately following invention of a Connect6 game, many game programs were developed aggressively. However, because the solution space of the Connect6 game is extremely large, the computation powers of current computers are quite insufficient to search all possible solutions. This paper therefore presents a proposal of a field programmable gate array (FPGA) Connect6 Solver with a two-stage pipelined evaluation exploiting numerous zero-evaluation functions to evaluate only a zero value and a small number of detailed evaluation functions which can evaluate all range. The FPGA Connect6 Solver implemented onto a Cyclone IV FPGA is able to defeat target software provided by the 2011 International Conference on Field-Programmable Technology (ICFPT) within the time limit of 1 s for each turn. In addition, the FPGA Connect6 Solver can defeat another JAVA-based software program with a similar algorithm. At that time, the operation speed of the FPGA Connect6 Solver is 764.2 times higher than that of the software operating on a personal computer (Vostro 220S; Dell Inc.) with a 3.16 GHz, Core 2 Duo processor (Intel Corp.).

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous reconfiguration contexts. However, fast reconfiguration and numerous reconfiguration contexts share a trade-off relation on current VLSIs. Therefore, Optically Reconfigurable Gate Arrays (ORGAs) have been developed to resolve this dilemma. An ORGA architecture allows many configuration contexts by exploiting the large storage capacity of a holographic memory and fast reconfiguration using wide-bandwidth optical connections between a holographic memory and a programmable gate array VLSI. In addition, Dynamic Optically Reconfigurable Gate Arrays (DORGAs) using a photodiode memory architecture have already been developed to realize a high-gate-density VLSI. Therefore, this article presents the first demonstration of a nanosecond-order configuration of a nine-context DORGA architecture. Moreover, this article presents a proposal of a reconfiguration period adjustment technique to control each reconfiguration period to its best setting.

Recently, for autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. To date, analog-type vision chips and digital vision chips have been developed. Nevertheless, even now, to realize such high-speed real-time image recognition operation is extremely difficult. Therefore, to realize a high-speed real-time image-recognizable vision chip, this paper presents a proposal for a dynamically reconfigurable vision chip architecture. In addition, some experimental results are reported.

This report presents an Othello Solver based on a 32-bit original soft-core Multiple Instruction stream, Multiple Data stream (MIMD) processor array targeting a single field programmable gate array (FPGA), Cyclone II (EP2C70D896C6N), on a DE2 Development and Education Board (Altera Corp.). The solver can execute a move-checking operation, a disc flipping operation, a move selection operation, an evaluation operation, and an alpha-beta pruning operation. The solver system includes a universal asynchonous receiver transmitter (UART) inside the FPGA and uses a RS-232C driver on the board so that the solver system can communicate with a personal computer or another FPGA according to the 2010 International Conference on Field Programmable Technology (FPT) competition specifications. The solver can win all skill levels of a target software provided from the FPT conference within the time limit of 1/40 s. This report presents estimates the solver's performance based on the implementation results.

Demand for use of FPGAs in space is increasing to support hardware repair and hardware update functions in addition to software repair and update functions in spacecraft, satellites, space stations, and other applications. Under a space radiation environment, embedded devices must allow for incidence of high-energy charged particles. Such incidence can cause single or multi-event latch-up (S/MEL)-associated troubles and single or multi-event upset (S/MEU)-associated temporary failures. Although an FPGA, because of its programmability, presents the advantageous capabilities of recovering from and updating after S/MEL-associated troubles, the FPGA can not guard itself completely from S/MEU-associated temporary failures that might arise on its configuration SRAM. This paper therefore presents a proposal for a 64-context MEMS optically reconfigurable gate array that can support a remotely updatable hardware function, can quickly repair S/MEL-associated permanent failures, and can perfectly guard itself from S/MEU-associated temporary failures that can occur in a space radiation environment.

To date, optically reconfigurable gate arrays (ORGAs) have been developed to realize large virtual gates and to increase gate array performance by combining a holographic memory with a programmable gate array. Among such studies, a 16-context ORGA architecture with nanosecond-order reconfiguration capability has already been demonstrated. However, its reconfiguration contexts are too few to execute large real-time operations. This paper therefore presents a proposal of a more advanced 100-context ORGA architecture in addition to related experimental results.

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of processors. Dynamic reconfiguration has two important prerequisites: fast reconfiguration and numerous reconfiguration contexts. Unfortunately, fast reconfigurations and numerous contexts share a tradeoff relation on current VLSIs. Therefore, optically reconfigurable gate arrays were developed to resolve this dilemma. Optically reconfigurable gate arrays can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Furthermore, optically reconfigurable gate arrays can realize rapid reconfiguration using large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. This paper presents the fastest 317-657 ns reconfiguration demonstration of a 16-context optically reconfigurable gate array architecture.

The world's largest 11,424 gate-count dynamic optically reconfigurable gate array VLSI chip, which is based on the use of junction capacitance of photodiodes as configuration memory, has been fabricated. The size and process of the VLSI chip are, respectively, a 96.04 mm2and a 0.35 mum-3metal CMOS process technology. To clarify the availability of the VLSI, this paper shows an experimental result of a long retention time of its photodiode memory architecture.

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits on its programmable gate array. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous contexts. However, fast reconfigurations and numerous contexts share a trade-off relation on current VLSIs. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to resolve this dilemma. ORGAs can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Also, ORGAs can realize fast reconfiguration through use of large bandwidth optical connections between a holographicmemory and a programmable gate array VLSI. This paper presents the world's first demonstration of an ORGA with micro electro mechanical system's (MEMS) holographic memory.

Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSIs. Consequently, ORGAs with more than tera-gate capacity will be realized by exploiting the storage capacity of a holographic memory. However, compared with current field programmable gate arrays (FPGAs), conventional ORGAs have an important shortcoming: they are not reprogrammable after fabrication because, to reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, reprogrammed outside of the ORGA package using a holographic memory writer, and then implemented onto the ORGA package with high precision beyond the capability of manual assembly. To remove that daunting problem, this paper presents a nine-context programmable ORGA and its writer. Furthermore, this paper presents discussion of the availability of this architecture and future plans based on experimental results.

Optically differential reconfigurable gate arrays (ODRGAs) have been developed to achieve rapid reconfiguration and numerous reconfiguration contexts. Although fast reconfiguration experiments of a four-context ODRGA have been presented in earlier reports, the number of configuration contexts was insufficient for dynamic reconfiguration applications. Therefore, we have developed a more advanced nine-context ODRGA system. This paper presents fast 86.2 ns reconfiguration experiments using a nine-context ODRGA architecture and discusses plans for future work.

Reconfiguration applications based on reconfigurable devices present new computational paradigms because, by increasing the reconfiguration frequency of reconfigurable devices, their activity and performance can be improved dramatically. Recently, optically reconfigurable gate arrays (ORGAs) with a holographic memory have been developed to realize rapid reconfigurations and numerous reconfiguration contexts. In addition, optically differential reconfigurable gate arrays (ODRGAs) have been developed to accelerate optical reconfigurations of conventional ORGAs. However, fast configuration experiments under multiple contexts exploiting the ODRGA architecture have never been reported. Therefore, this paper presents a four-context ODRGA system and experimental results that elucidate aspects of fast reconfiguration. The advantage of the ODRGA architecture is discussed based on those results.

This paper presents a novel inversion / non-inversion zero-overhead dynamic optically reconfigurable gate array that can extract good factors from architectures of both optically differential reconfigurable gate arrays and dynamic optically reconfigurable gate arrays. A full VLSI design using a 0.35 mum CMOS process technology is presented. Based on that presentation, three factors are discussed: gate density, reconfiguration frequency per unit of laser power, optical power consumption.

In previously proposed ORGAs, the optical reconfiguration period was designed to be constant by assuming a worst-case reconfiguration speed. However, the diffraction efficiency of a holographic memory differs depending on the number of bright bits included in a configuration context. Therefore, previous ORGAs can not fully exploit reconfiguration performance. For that reason, this paper presents a proposal for an analog reconfiguration-period adjustment technique for ORGAs to reduce each reconfiguration period. The advantages are then discussed herein based on experimental results obtained using an ORGA system on which the technique is adopted.

A DORGA architecture has been proposed to increase gate density. It uses the junction capacitance of photo-diodes as dynamic memory, thereby obviating the static configuration memory. This paper presents the worldpsilas largest 11,424 gate-count dynamic optically reconfigurable gate array (DORGA) VLSI fabricated on a 96.04 mm2chip using a 0.35 mum three-metal CMOS process technology and a perfect optical system using a holographic memory. The advantages of this architecture are discussed in relation to the results described herein.

Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count by adding a holographic memory onto a programmable gate array VLSI. However, in ORGAs, although a large virtual gate count can be realized by exploiting the large capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is still important to increase the instantaneous performance. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-gate-count ORGA-VLSIs. Therefore, to increase the gate density, a dynamic optically reconfigurable gate array (DORGA) architecture has been proposed. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, although only a 1.83–1.89 ms single-context holographic configuration and a retention time of 3.49−5.61 s of DORGA architecture have been confirmed, the performance at nanosecond-scale reconfiguration with a multi-context DORGA architecture has never been analyzed. Therefore, this paper presents the experimental result of a 937.5 ns multi-context holographic configuration and a 30.75 μs retention time of DORGA architecture. The advantages of this architecture are discussed in relation to the results of this study.

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array to realize fast reconfiguration and numerous reconfiguration contexts. Along with such advantages, ORGAs have high defect tolerance. They consist simply of a holographic memory, a laser diode array, and a gate array VLSI. Even if a gate array VLSI includes defective areas, the perfectly parallel programmable capability of ORGAs enables perfect avoidance of those defective areas through alternative use of other non-defective areas. Moreover, holographic memories to store contexts are known to have high defect tolerance because each bit of a reconfiguration context can be generated from the entire holographic memory. Moreover, the damage of some fraction rarely affects its diffraction pattern or a reconfiguration context. Therefore, ORGAs are very robust against component defects in devices such as laser arrays, gate arrays, and holographic memory, and are particularly useful for space applications, which require high reliability. However, to date, the degree to which defects in a holographic memory affects holographic configurations has never been analyzed. Therefore, this paper describes analysis results of defect limitations of holographic configurations.

A zero-overhead dynamic optically reconfigurable gate array VLSI (ZO-DORGA-VLSI) has been developed. It is based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory and removing static memory function to store a context. In this paper, the performance of a 1,632 ZO-DORGA-VLSI, which was fabricated using a 0.35 mum - 4.9 mm square CMOS process chip, is presented. In addition, the design of an over 10,000 ZO-DORGA-VLSI is presented.

To date, holographic configuration speeds have remained limited to 16 mus because of issues related to the architecture of optically reconfigurable gate array VLSIs (ORGA-VLSIs). Therefore, to improve the issue, optically differential reconfigurable gate array VLSIs (ODRGA-VLSIs) have been developed and have achieved zero-overhead and nanosecond optical reconfiguration. Moreover, the architecture of an ODRGA-VLSI has the advantage of accelerating the reconfiguration speed compared to that of other ORGAs. However, nanosecond holographic configurations and, in particular, rapid holographic reconfiguration exploiting the advantages of ODRGA-VLSIs have not been reported. Therefore, this paper presents results of the world's fastest 62.5 ns holographic reconfiguration, exploiting advantages of the ODRGA-VLSI.

To increase gate density, a dynamic optically re-configurable gate array (DORGA) architecture has been proposed that uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, estimation of a perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. This paper presents a perfect DORGA architecture including a holographic memory. The performances of the DORGA architecture, in particular the reconfiguration context retention time, were analyzed experimentally. The advantages of this architecture are discussed in relation to the results of this study.

Optically reconfigurable gate arrays (ORGAs) offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSIs by exploiting the large storage capacity of a holographic memory. The first ORGA was developed to achieve rapid reconfiguration and a number of reconfiguration contexts; it consisted of a gate array VLSI, a holographic memory, and a laser diode array. The ORGA achieved a 16 mus to 20 mus reconfiguration period that was faster than that of FPGAs, with 100 reconfiguration contexts. However, the ORGA requires the gate array to halt during reconfiguration. Therefore, the ORGA cannot be reconfigured frequently because of the associated reconfiguration overhead. On the other hand, new ORGA-VLSIs that have less than 10 ns reconfiguration capability without any related overhead have already been fabricated. However, to date, a multi-holographic reconfiguration system that is suitable for such rapidly reconfigurable ORGA-VLSIs without any overhead has never been developed. For such realization, this paper proposes a four-context ORGA architecture and a multi-context holographic memory recording system used for it. In addition, experimentally demonstrated results of recording a holographic memory and reconfiguring an ORGA-VLSI are described.

Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array that can achieve rapid reconfiguration for numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed by a laser diode array. It is noteworthy that ORGA-VLSIs that can be reconfigured in less than 10 ns without any overhead have already been fabricated. However, up to now, a multi-holographic reconfiguration system that is suitable for such fast-reconfigurable ORGA-VLSIs without any overhead has never been developed. As the first step toward such realization, a multi-context component is demonstrated experimentally using a liquid crystal spatial light modulator and a pulse laser. This paper describes experimental results and plans for future work.

This paper presented the design of the largest 476-gate count DORGA fabricated by using 0.35 mum three-metal CMOS technology. In the case of reconfiguring DORGA at 100MHz, the required optical power was estimated 2.24 W. At that time, the reconfiguration data transfer rate of the DORGA VLSI chip reaches 369.6 Gbit/s

Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array. The gate array of ORGAs is optically reconfigured using diffraction patterns from a holographic memory that is addressed by a laser diode array. In previously proposed ORGAs, the optical reconfiguration speed has been designed to be constant by assuming a worst-case reconfiguration speed. However, the diffraction efficiency of a holographic memory varies depending on the pattern of reconfiguration contexts that is recorded in it. Therefore, this paper proposes a reconfiguration speed adjustment technique for ORGAs to accelerate the reconfiguration speed. In addition, the advantages are discussed from some simulation results of a holographic memory and the experimental results of a fabricated gate array VLSI.

Optically reconfigurable gate arrays (ORGAs) are a type of field programmable gate array (FPGA). However, unlike FPGAs, an ORGA can quickly be reconfigured optically using external optical memories and optical connections. Recently, various types of ORGAs have been developed. However, their gate counts were not satisfactory compared with those of FPGAs. Therefore, to improve the gate density of conventional ORGAs, a dynamic ORGA (DORGA) architecture that can remove static memory functions to store a configuration context has been proposed. The DORGA architecture offers not only the advantages of a high gate count, but also the advantage of low reconfiguration power consumption. To date, its power consumption has never been clarified. For that reason, this paper presents measurement results of the optical reconfiguration power consumption of a DORGA-VLSI chip. In addition, the power consumption advantages of the DORGA architecture are clarified through comparison with other ORGAs

Optically reconfigurable gate arrays (ORGAs) offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSIs by exploiting the large storage capacity of holographic memory. We developed an optically differential reconfigurable gate array (ODRGA-VLSI) with no overhead and fast reconfiguration capability. This paper presents the results of development of a perfect optical reconfigurable system with the ODRGA-VLSI chip and holographic memory. Experimental results of the reconfiguration procedure and circuit performance on a gate array are also presented

A new optically differential reconfigurable gate array (ODRGA) is proposed to reduce configuration power consumption. The ODRGA has a simple architecture that adds a small circuit to conventional optically reconfigurable gate arrays (ORGAs) and uses differential configuration data stored in an optical holographic memory. In this paper configuration power consumption of ORGAs is estimated theoretically. Based on results, we show an estimation of configuration power consumption and comparative area occupied by the configuration circuit for ODRGA and conventional ORGAs.