EDBT 2026 Demo / reviewers in the wild / expert
Bic Schediwy
dblp:41/7016
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1988
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Graphics, computer vision, multimedia, augmented reality and games · 1Human-computer interaction and ubiquitous computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
GPUs and heterogeneous computing · 50% Integrated circuit design · 50% | |
| Computer graphics and multimedia
1 paper |
Rendering · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing
graphics accelerator |
0.0 | 1 | 1988 | The triangle processor and normal vector shader: a VLSI system for high performance graphics · SIGGRAPH 1988 |
Integrated circuit design
VLSI design |
0.0 | 1 | 1988 | The triangle processor and normal vector shader: a VLSI system for high performance graphics · SIGGRAPH 1988 |
Rendering › shading
phong shading |
0.0 | 1 | 1988 | The triangle processor and normal vector shader: a VLSI system for high performance graphics · SIGGRAPH 1988 |
Methods — techniques the papers use, named apart from their topics
triangle processor pipeline · 0.0normal vector shader · 0.0anti-aliasing · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1988 | The triangle processor and normal vector shader: a VLSI system for high performance graphicsabstractCurrent affordable architectures for high-speed display of shaded 3D objects operate orders of magnitude too slowly. Recent advances in floating point chip technology have outpaced polygon fill time, making the memory access bottleneck between the drawing processor and the frame buffer the most significant factor to be accelerated. Massively parallel VLSI system have the potential to bypass this bottleneck, but to date only at very high cost. We describe a new more affordable VLSI solution. A pipeline of triangle processors rasterizes the geometry, then a further pipeline of shading processors applies Phong shading with multiple light sources. The triangle processor pipeline performs 100 billion additions per second, and the shading pipeline performs two billion multiplies per second. This allows 3D graphics systems to be built capable of displaying more than one million triangles per second. We show the results of an anti-aliasing technique, and discuss extensions to texture mapping, shadows, and environment maps. Michael Deering, Stephanie Winner, Bic Schediwy, Chris Duffy, Neil Hunt |
SIGGRAPH | 3 |