We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern generator (ATPG) and are encoded as linear feedback shift register (LFSR) initial values (seeds); one or more patterns can be encoded into a single LFSR seed. During test application, seeds are loaded into the LFSR with no cycle overhead. The method presented achieves reductions of at least 100x in test data and 10x in tester cycles compared to deterministic ATPG while maintaining complete fault coverage, as confirmed by experimental results on industrial designs.

Fault simulation is a computer-intensive problem. Parallel processing is one method to reduce simulation time. In this paper, we discuss a technique to partition the fault set for fault-parallel simulation on multiple processors. When applied statically, the technique can scale well for up to 32 processors. The fault-set partitioning technique is simple and can itself be parallelized. Existing uniprocessor algorithms, based on parallel-pattern simulation, can be used for multiprocessor simulation without modification. Therefore, the techniques can be used effectively on a low-cost parallel resource such as a network of workstations.

We present a new multiprocessor sequential circuit fault simulator, Zamlog, based on a novel uniprocessor simulator, Zambezi. Both the fault and test sets are partitioned for multiprocessor simulation. The parallelization technique, designed to preserve the efficiency of Zambezi, is simple to implement and has low communication requirements. Experimental results indicate that Zamlog can obtain speedups of up to 95. The speedups obtained and the scalability are between 3 and 10 times better than any reported in the literature. Furthermore, the speed-ups obtained are with respect to a uniprocessor algorithm which is superior, by an average of 40%, to those used to gauge the speed-ups of previous parallel systems.

Sequential circuit fault simulators use the multiple bits in a computer data word to accelerate simulation. We introduce, and implement, a new sequential circuit fault simulator, a parallel pattern parallel fault simulator, ZAMBEZI, which simultaneously simulates multiple faults with multiple vectors in one data word. ZAMBEZI is developed by enhancing the control flow, of existing parallel pattern algorithms. For a very wide range of benchmark circuits, compared to parallel fault and parallel pattern simulators, ZAMBEZI offers either the best, or very close to the best, uniprocessor performance. ZAMBEZI also offers superior performance when parallelized.

Fault simulation is a compute intensive problem. Data parallel simulation on multiple processors is one method to reduce fault simulation time. We discuss a novel technique to partition the fault set for data parallel fault simulation. When applied statically, the technique can scale well for up to eight processors. The fault set partitioning technique is simple, can itself be parallelized, and can be implemented with extreme ease. Therefore, the technique can be used on a low cost parallel resource, such as a network of workstations.

We present a new technique for mapping the backpropagation algorithm on hypercube and related architectures. A key component of this technique is a network partitioning scheme called checkerboarding. Checkerboarding allows us to replace the all-to-all broadcast operation performed by the commonly used vertical network partitioning scheme, with operations that are much faster on the hypercubes and related architectures. Checkerboarding can be combined with the pattern partitioning technique to form a hybrid scheme that performs better than either one of these schemes. Theoretical analysis and experimental results on nCUBE and CM5 show that our scheme performs better than the other schemes, for both uniform and nonuniform networks.>

The authors discuss the requirements of learning for generalization, where the traditional methods based on gradient descent have limited success. A stochastic learning algorithm based on simulated annealing in weight space is presented. The authors verify the convergence properties and feasibility of the algorithm. An implementation of the algorithm and validation experiments are described.>