Modular adders are essential components in finite field arithmetic, serving as key components in public-key cryptographic algorithms like Elliptic Curve Cryptography (ECC) and Post-Quantum Cryptography (PQC). Naïve implementation of modular adders, due to two cascaded adders with large operand bit widths struggle to meet high-frequency requirements. On the other hand, parallel implementations, while faster, demand excessive resources and power, making them impractical for many applications. This paper introduces a novel modular addition algorithm leveraging a novel operand representation based on the two-valued digit encoding (Twit). In this approach, each operand is represented as an n-bit unsigned number augmented by a Twit value {0,±δ}. The algorithm efficiently computes modular addition by speculating and dynamically adjusting the twit value in the result, achieving both computational and resource efficiency. The proposed design has been implemented on a Xilinx 7-series FPGA, demonstrating superior performance in achieving high operating frequencies (i.e., 8% to 36% depending on operand bit widths) while significantly reducing resource utilization (i.e., >36%). In addition to extensive analytical and synthesis-based evaluations, we further demonstrate the benefits of the proposed adder within application-level cryptographic datapaths (ECC and PQC).

Modular adders are essential arithmetic components in Residue Number System (RNS)-based applications, including digital signal processing, cryptography, and machine learning. These applications consistently push the boundaries of dynamic range (DR) and operating frequency, making the design of efficient generic modular adders a critical and evolving challenge. This paper presents a novel algorithm for modulo$-(2^{n}\pm \delta)$addition, where$\delta$is an integer within the range$0\leq\delta\leq 2^{n-1}-1$. The proposed approach leverages a two-valued digit (twit) for encoding the value of$\pm\delta$and uses a faithful representation of operands. In this representation, each operand is encoded as an n-bit unsigned number augmented by a twit value$\{0,\pm\delta\}$. The algorithm efficiently performs modular addition by speculating and adjusting the twit value in the addition result. When the result exceeds the modulus, it subtracts$\mathrm{z}^{n}\pm\delta$by ignoring the carry-out and adjusting the speculated twit value. This adjustment is achieved through an XOR operation between the carry-out and the speculated twit value, simplifying the modular reduction process. The proposed design has been synthesized for practical n$(4\leq n\leq 16$using a FreePDK 45 nm process. The results demonstrate superior performance across key metrics such as delay, area, and power consumption compared to previous designs, highlighting the efficacy and scalability of the approach.