Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Sanle Zhao

dblp:412/2647 · DBLP profile ↗
← Back
4ranked-venue papers
2as first author
4since 2021 · last 2026
0009-0002-9035-8673ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Memory systems · 100%
Artificial intelligence
1 paper
Efficient and distributed learning · 67% Language models and text generation · 33%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › cache management
cache replacement
1.722025
CMCache: An Adaptive Cross-Level Data Placement Method for Multilevel Cache · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
LAShards: Low-Overhead and Self-Adaptive MRC Construction for Non-Stack Algorithms · IEEE Trans. Computers 2025
Machine learning › Efficient and distributed learning
inference efficiency
1.012026
HitKV: Activation Frequency Knows Which Tokens Are Important · AAAI 2026
Machine learning › Efficient and distributed learning › KV cache management
KV cache compression
1.012026
HitKV: Activation Frequency Knows Which Tokens Are Important · AAAI 2026
Natural language and speech › Language models and text generation › language modeling › long-context language modeling › context utilization
long-context modeling
1.012026
HitKV: Activation Frequency Knows Which Tokens Are Important · AAAI 2026
Memory systems
cache
0.912025
LAShards: Low-Overhead and Self-Adaptive MRC Construction for Non-Stack Algorithms · IEEE Trans. Computers 2025
Memory systems
cache management
0.912025
CMCache: An Adaptive Cross-Level Data Placement Method for Multilevel Cache · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Memory systems › cache management
shared cache management
0.312025
LAShards: Low-Overhead and Self-Adaptive MRC Construction for Non-Stack Algorithms · IEEE Trans. Computers 2025

Methods — techniques the papers use, named apart from their topics

layer-aware memory allocation · 1.0attention scoring · 1.0spatially hashed sampling · 0.9miniature simulation · 0.9locality-aware sampling · 0.9adaptive placement strategy · 0.9
YearPublicationVenuePosition
2026 HitKV: Activation Frequency Knows Which Tokens Are Important
abstract
The demand for long-context processing in large language models (LLMs) continues to escalate alongside rapid advancements in their capabilities. However, the intermediate attention keys and values (KV cache) employed to avoid re-computations, also grow linearly with sequence length, far exceeding the memory capacity of consumer-grade GPUs. Consequently, many studies have proposed KV cache compression methods that evict unimportant tokens based on variant attention scoring strategies. These methods typically retain the KV pairs of the top-k scoring tokens under a fixed memory budget. However, they still face several limitations. First, they disregard the activation frequency of tokens, specifically the count of times tokens achieve top-k scores in the attention distribution of following tokens. The methods based on variant attention scores may incorrectly evict some high-activation-frequency yet low final-scoring tokens. Second, the activation frequency exhibits different distribution patterns across layers and tasks. Neglecting these differences negatively impacts model performance and task adaptability. Our analysis of the actual token activation frequency and its unique characteristics across layers and task types reveals potential opportunities to address these issues. In this paper, we propose HitKV, which employs hit rates to directly characterize token activation frequencies, enabling adaptive layer-aware and task-aware KV cache eviction under the uniform memory allocation strategies. Also, HitKV can be easily integrated into layer-specific memory allocation methods. Experimental results demonstrate that HitKV maintains model performance with preserving only 3% of the KV cache, achieves high-quality generation outputs in long-text generation tasks, and delivers 4× throughput improvement over baselines.
Sanle Zhao, Yujuan Tan, Jing Yu 0026, Zhuoxin Bai, Zongjie Wang, Ao Ren
AAAI1
2025 DualSpar: A Dual-Granularity Memory Framework with Adaptive Sparsity for Efficient LLM Inference
abstract
The block-based inference engine, powered by noncontiguous key-value (KV) cache management, has emerged as a new paradigm for large language model (LLM) inference due to its efficient memory utilization. However, in large-batch, longcontext workloads, the substantial demand for KV cache remains a major bottleneck in inference performance. Existing research leverages the sparsity of the attention mechanisms by removing non-critical tokens to limit the KV cache size. However, we observe that in block-based inference engines, current sparse methods require defragmentation after token removal to maintain tensor continuity, incurring significant overhead. Additionally, we find a correlation between request length and sparsity potential, yet existing methods apply a uniform sparsity strategy at batch level without dynamic adjustment. To address these, we propose DualSpar, a novel sparse KV cache framework with dual-granularity memory and adaptive sparsity strategy. First, it binds token importance to KV cache block granularity, achieving low-overhead pre-consolidation. Second, it incorporates system load and request length into sparsity decision, fully exploiting the sparse potential of different requests while reducing the queuing latency in large-batch processing. Evaluations show that DualSpar achieves up to a 3.16× throughput improvement, a 3.75× faster time-to-first-token (TTFT), and an 87.2% reduction in defragmentation overhead while maintaining high accuracy.
Yujuan Tan, Zhuoxin Bai, Sanle Zhao, Yujiao Wang, Zongjie Wang, Ao Ren, Kan Zhong
ICCD4
2025 LAShards: Low-Overhead and Self-Adaptive MRC Construction for Non-Stack Algorithms
abstract
Shared cache systems have become increasingly crucial, especially in cloud services, where the Miss Ratio Curve (MRC) is a widely used tool for evaluating cache performance. The MRC depicts the relationship between the cache miss ratio and cache size, indicating how cache performance trends with varying cache sizes. Recent advancements have enabled efficient MRC construction for stack replacement policies. For non-stack policies, miniature simulation downsizes the actual cache size and data stream through spatially hashed sampling, providing a general method for MRC construction. However, this approach still faces significant challenges. Firstly, constructing an MRC requires numerous mini-caches to obtain miss ratios, consuming significant cache resources, leading to tremendous memory and computing overhead. Secondly, it cannot adapt to the dynamic I/O workloads, resulting in less precise MRC.To address these issues, we propose LAShards, a low-overhead and self-adaptive MRC construction method for non-stack replacement policies. The key idea behind LAShards is to exploit the locality and burstiness in access patterns. It can statically reduce memory usage and dynamically adapt to workloads. Compared to previous works, LAShards can save up to 20× of memory resources, and increase throughput by up to 10×.
Sanle Zhao, Yujuan Tan, Zhaoyang Zeng, Jing Yu 0026, Zhuoxin Bai, Ao Ren, Xianzhang Chen, Duo Liu 0002
IEEE Trans. Computers1
2025 CMCache: An Adaptive Cross-Level Data Placement Method for Multilevel Cache
abstract
Multilevel cache systems enhance I/O performance by optimizing data placement across various cache levels from a global perspective. However, existing methods often struggle to place data at the optimal cache level promptly due to their reliance on historical access patterns and inflexible placement strategies. These methods face two main challenges: 1) for already cached data with sufficient access history, existing approaches only optimize movement between adjacent cache levels, potentially delaying data arrival at its globally optimal cache level and leading to unnecessary bandwidth consumption and increased latency and 2) for newly entered data without access history, current methods cannot accurately predict their future hotness and simply place them at a fixed cache level (i.e., first or final level), overlooking future accesses of new data and potentially resulting in high cache miss rates or cache pollution. To address these issues, we propose CMCache, an adaptive cross-level data placement method for multilevel cache. CMCache applies distinct placement strategies for cached and new data to reach the optimal level timely, considering their different characteristics. It also logically divides cache space into two sections to manage cached and new data separately, dynamically adjusting section sizes based on access patterns. This approach significantly improves data placement efficiency, achieving up to an 89% reduction in miss rates and a 79% decrease in average response times compared to existing methods.
Zhaoyang Zeng, Yujuan Tan, Zhulin Ma, Sanle Zhao, Duo Liu 0002, Xianzhang Chen, Ao Ren
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5