Jixuan Tang

dblp:412/5780 · DBLP profile ↗
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3ranked-venue papers
0as first author
3since 2021 · last 2026
0009-0008-1933-2079ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Memory systems · 65% GPUs and heterogeneous computing · 35%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache design
1.922026
HIVE+: An Enhanced High-Priority Victim Cache to Accelerate GPU Memory Accesses · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses · DAC 2025
GPUs and heterogeneous computing › GPU memory
GPU memory hierarchy
1.922026
HIVE+: An Enhanced High-Priority Victim Cache to Accelerate GPU Memory Accesses · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses · DAC 2025
Memory systems › cache › cache organization
victim cache
1.922026
HIVE+: An Enhanced High-Priority Victim Cache to Accelerate GPU Memory Accesses · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses · DAC 2025
Memory systems
cache
1.012026
HIVE+: An Enhanced High-Priority Victim Cache to Accelerate GPU Memory Accesses · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
GPUs and heterogeneous computing
GPU memory access
1.012026
HIVE+: An Enhanced High-Priority Victim Cache to Accelerate GPU Memory Accesses · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Memory systems › cache management
cache replacement
0.312026
HIVE+: An Enhanced High-Priority Victim Cache to Accelerate GPU Memory Accesses · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Memory systems › memory hierarchy
cache hierarchy
0.312025
HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses · DAC 2025

Methods — techniques the papers use, named apart from their topics

victim cache · 1.0high-priority caching · 1.0
YearPublicationVenuePosition
2026 HIVE+: An Enhanced High-Priority Victim Cache to Accelerate GPU Memory Accesses
Yuhan Tang, Sheng Ma, Hanqing Li, Shengbai Luo, Jixuan Tang, Siqing Fu, Lizhou Wu
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.7
2025 HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
abstract
The victim cache was originally designed as a secondary cache to handle misses in the L1 data (L1D) cache in CPUs. However, this design is often sub-optimal for GPUs. Accessing the high-latency L1D cache and its victim cache can lead to significant latency overhead, severely degrading the performance of certain applications. We introduce HIVE, a high-priority victim cache designed to accelerate GPU memory accesses. HIVE handles memory requests first, before they reach the L1D cache. Our experimental results show that HIVE achieves an average performance improvement of $\mathbf{7 7. 1 \%}$ and $\mathbf{2 1. 7 \%}$ compared to the baseline and the state-of-the-art architecture, respectively.
Yuhan Tang, Sheng Ma, Hanqing Li, Shengbai Luo, Jixuan Tang, Lizhou Wu
DAC7
2025 NeuroPDE: A Neuromorphic PDE Solver Based on Spintronic and Ferroelectric Devices
abstract
In recent years, new methods for solving partial differential equations (PDEs) such as Monte Carlo random walk methods have gained considerable attention. However, due to the lack of hardware-intrinsic randomness in the conventional von Neumann architecture, the performance of PDE solvers is limited. In this paper, we introduce NeuroPDE, a hardware design for neuromorphic PDE solvers that utilizes emerging spintronic and ferroelectric devices. NeuroPDE incorporates spin neurons that are capable of probabilistic transmission to emulate random walks, along with ferroelectric synapses that store continuous weights non-volatilely. The proposed NeuroPDE achieves a squared error of less than 1e-2 compared to analytical solutions when solving diffus3.48× to 315× speedup in execution time and an energy consumption advantage of 2.7× to 29.8× over advanced CMOS-based neuromorphic chips. By leveraging the inherent physical stochasticity of emerging devices, this study paves the way for future probabilistic neuromorphic computing systems.
Siqing Fu, Lizhou Wu, Chunyuan Zhang, Sheng Ma, Yuhan Tang, Jixuan Tang
ICCAD8