Demo Data from EDBT 2026 / reviewers in the wild / expert
Lukas Neef
dblp:414/3679
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2025
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Embedded and real-time systems · 87% GPUs and heterogeneous computing · 13% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Embedded and real-time systems › embedded hardware platform
FPGA-based embedded platform |
0.9 | 1 | 2025 | Work-in-Progress: Toward Real-Time Cross-ISA Execution on the AMD Embedded+ Architecture · RTSS 2025 |
Embedded and real-time systems › embedded hardware platform
heterogeneous embedded platform |
0.9 | 1 | 2025 | Work-in-Progress: Toward Real-Time Cross-ISA Execution on the AMD Embedded+ Architecture · RTSS 2025 |
GPUs and heterogeneous computing › heterogeneous architecture
heterogeneous processors |
0.3 | 1 | 2025 | Work-in-Progress: Toward Real-Time Cross-ISA Execution on the AMD Embedded+ Architecture · RTSS 2025 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Work-in-Progress: Toward Real-Time Cross-ISA Execution on the AMD Embedded+ ArchitectureabstractEmerging embedded platforms increasingly rely on heterogeneous processing units to address diverse performance and energy requirements. The recently introduced AMD Embedded+ architecture reflects this trend by interconnecting via PCIe on the same motherboard one AMD x86 host processor with one Arm AArch64+FPGA complex. This implementation is another step forward towards a more compact heterogeneousISA platform designed with embedded applications in mind. While cross-ISA execution has been explored in the past with a focus on performance, programmability, and energy efficiency, its potential for embedded and predictable real-time workloads remains largely unexplored. In this paper, we start exploring such potential by investigating the real-time capabilities of the first commercial platform based on the AMD Embedded+ architecture: the Sapphire Edge+. We (1) outline key research challenges and real-time use-cases, (2) discuss suitable software architectures for the use-cases and highlight associated trade-offs, and (3) report an initial assessment of the potential of such architectures and use-cases via an experimental evaluation of latency and bandwidth on the real hardware. Lukas Neef, Daniele Ottaviano, Denis Hoornaert, Alexander Züpke, Marco Caccamo, Andrea Bastoni |
RTSS | 1 |