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Sriparna Mandal

dblp:414/3789 · DBLP profile ↗
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1ranked-venue papers
1as first author
1since 2021 · last 2026
0000-0001-7776-7021ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
bioinformatics accelerator
1.012026
Hardware Accelerator for Short-Read DNA Sequence Alignment Using Burrows-Wheeler Transformation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Hardware accelerators and domain-specific architectures › bioinformatics accelerator
sequence alignment accelerator
1.012026
Hardware Accelerator for Short-Read DNA Sequence Alignment Using Burrows-Wheeler Transformation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026

Methods — techniques the papers use, named apart from their topics

parallel search · 1.0burrows-wheeler transformation · 1.0binary search · 1.0
YearPublicationVenuePosition
2026 Hardware Accelerator for Short-Read DNA Sequence Alignment Using Burrows-Wheeler Transformation
abstract
Next-generation sequencing deals with exponential growth in sequence databases; the primary challenge is aligning short-read sequences in a time-efficient manner. Despite numerous efforts in contemporary research, they unfortunately face trade-off issues related to time, power consumption, and resource constraints. A hardware accelerator is presented utilizing the Burrows-Wheeler Transformation without involving any sequence terminator to perform short-read sequencing at hardware speed, which eases additional storage, operations, and power consumption. Further, a hardware-based binary search scheme is introduced to reduce power consumption of the accelerator. As an alternative, a parallel searching mechanism is introduced to accomplish the searching operation in a single clock-cycle. The accelerator is evaluated for 64-to-256 nucleotide reference sequences and 32-to-56 nucleotide query sequences. The parallel search scheme consumes ≈11% less time than the binary search-based scheme, consuming ≈1.6–3.7% and ≈4.5–23% more resources and power. While comparing the accelerator with the with-terminator method, it achieves ≈31.01–33.13% gain in processing time, ≈31.28–34.47% saving in hardware resource, ≈33.08–33.29% saving in storage, and ≈14.03–50.79% gain in power consumption. Finally, this accelerator exhibits a gain of ≈52× in throughput without involving any terminator and external memory compared to state-of-the-art architectures.
Sriparna Mandal, Surajeet Ghosh
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1