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Chetal Choppali Sudarshan

dblp:415/5093 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 64% Integrated circuit design · 28% Hardware reliability and fault tolerance · 8%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › system-level design
chiplet design
0.912025
Invited: EDA for Heterogeneous Integration · DAC 2025
Integrated circuit design
heterogeneous integration
0.912025
Invited: EDA for Heterogeneous Integration · DAC 2025
Electronic design automation
physical design
0.912025
Invited: EDA for Heterogeneous Integration · DAC 2025
Electronic design automation
design technology co-optimization
0.312025
Invited: EDA for Heterogeneous Integration · DAC 2025
Hardware reliability and fault tolerance › reliability physics
thermo-mechanical stress analysis
0.312025
Invited: EDA for Heterogeneous Integration · DAC 2025

Methods — techniques the papers use, named apart from their topics

multiphysics simulation · 0.9machine-learning-driven analysis · 0.9
YearPublicationVenuePosition
2025 Invited: EDA for Heterogeneous Integration
abstract
The advent of heterogeneous integration (HI) places new demands on EDA tooling. Building large systems requires (1) methods for chiplet disaggregation that map the system to smaller chiplets, working in conjunction with system-technology co-optimization to determine the right design decisions that optimize computation and communication, together with the choice of substrate and chiplet technologies; (2) multiphysics and multiscale analyses that incorporate thermomechanical aspects into performance analysis, ranging from fast machine-learningdriven analyses in early stages to signoff-quality multiphysics-based analysis; (3) physical design techniques for placing and routing chiplets and embedded active/passive elements on and within the substrate, including the design of thermal and power delivery solutions; and (4) underlying infrastructure required to facilitate HI-based design, including the design and characterization of chiplet libraries and the establishment of data formats and standards. This paper overviews these issues and lays out a set of EDA needs for HI designs.
Emad Haque, Pragnya Sudershan Nalla, Chetal Choppali Sudarshan, Divya Yogi, Chaitali Chakrabarti, Vidya A. Chhabria, Ramesh Harjani, Jeff Zhang 0001, Sachin S. Sapatnekar
DAC3