Demo Data from EDBT 2026 / reviewers in the wild / expert
Jiaxiang Zou
dblp:415/5169
· DBLP profile ↗
3ranked-venue papers
1as first author
3since 2021 · last 2026
0009-0000-8613-2589ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware accelerators and domain-specific architectures · 84% Emerging computing paradigms · 16% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Emerging computing paradigms
approximate computing |
0.9 | 1 | 2025 | April: Accuracy-Improved Floating-Point Approximation For Neural Network Accelerators · DAC 2025 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › transformer accelerator
LLM inference accelerator |
0.9 | 1 | 2025 | AxCore: A Quantization-Aware Approximate GEMM Unit for LLM Inference · MICRO 2025 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.9 | 1 | 2025 | AxCore: A Quantization-Aware Approximate GEMM Unit for LLM Inference · MICRO 2025 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator |
0.9 | 1 | 2025 | April: Accuracy-Improved Floating-Point Approximation For Neural Network Accelerators · DAC 2025 |
Hardware accelerators and domain-specific architectures
systolic array |
0.9 | 1 | 2025 | April: Accuracy-Improved Floating-Point Approximation For Neural Network Accelerators · DAC 2025 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
FPGA-based neural network accelerator |
0.3 | 1 | 2025 | April: Accuracy-Improved Floating-Point Approximation For Neural Network Accelerators · DAC 2025 |
Methods — techniques the papers use, named apart from their topics
systolic array · 0.9mixed-precision arithmetic · 0.9mitchell's logarithm · 0.9floating-point multiplication approximation · 0.9down-sampling-based compensation · 0.9co-design framework · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | UniCore: A Bit-Width Scalable GEMM Unit for Unified LLM Inference
Yonghao Chen, Jiaxiang Zou |
ISCA | 2 |
| 2025 | April: Accuracy-Improved Floating-Point Approximation For Neural Network AcceleratorsabstractNeural Networks (NNs) have achieved breakthroughs in computer vision and natural language processing. However, modern models are computationally expensive, with floating-point operations posing a major bottleneck. Floatingpoint approximation, such as Mitchell’s logarithm, enables floating-point multiplication using simpler integer additions, thereby improving hardware efficiency. However, its practical adoption is hindered by challenges such as precision degradation, efficient hardware integrations, and management of trade-offs between accuracy and resource efficiency. In this paper, we propose a hardware-efficient down-samplingbased compensation method to mitigate precision loss and a flexible bias mechanism to accommodate diverse data distributions in NN models. Building on this foundation, we design configurable systolic arrays optimized for NN accelerators. To further support practical adoption, we introduce April, a co-design framework that balances the accuracy and resource usage of generated synthesizable systolic arrays. Our FPGA-based evaluations demonstrate that April-generated systolic arrays reduce root mean square error (RMSE) by up to $\mathbf{9 6 \%}$ and achieve $\mathbf{3 4 \% -5 2 \%}$ area reduction even compared to INT8-based implementations while maintaining comparable or improved model accuracy. Our design is open-sourced at https://github.com/CLabGit/April Yonghao Chen, Jiaxiang Zou |
DAC | 2 |
| 2025 | AxCore: A Quantization-Aware Approximate GEMM Unit for LLM InferenceabstractLarge Language Models (LLMs) have become foundational to modern natural language processing, yet their immense computational and memory demands pose major obstacles for efficient inference.Transformer-based LLMs rely heavily on floating-point general matrix-matrix multiplication (FP-GEMM), which dominates both compute and bandwidth.In this paper, we introduce Ax-Core, a quantization-aware, approximate GEMM unit that combines weight-only quantization with floating-point multiplication approximation (FPMA) to deliver highly efficient and accurate LLM inference.Unlike traditional GEMM units, AxCore eliminates multipliers entirely, replacing them with low-bit integer additions in a novel systolic array.AxCore features several key innovations: (1) a mixedprecision FPMA-based processing element that supports direct computation on compressed weights and high-precision activations;(2) a lightweight accuracy preservation strategy, including subnormal number handling, error compensation, and format-aware quantization; and (3) a set of systolic array optimizations, including shared correction and normalization logic.Evaluations on opensource LLMs show that AxCore achieves up to 6.3×-12.5×higher compute density than conventional FP GEMM units.Compared to state-of-the-art INT4-based accelerators, FIGLUT and FIGNA, AxCore improves compute density by 53% and 70%, respectively, while also delivering lower perplexity.AxCore is opensourced at: https://github.com/CLab Jiaxiang Zou, Yonghao Chen |
MICRO | 1 |