Approximate multipliers have widely been used in error-resilient applications with hardware-efficient and relaxed precision requirements, such as multimedia signal processing and deep learning. Aiming to achieve improvements in power efficiency and performance, approximate multipliers are generally designed by simplifying the implementation circuits. However, the redundant switching activities (also known as glitches) due to unbalanced signal paths are seldom considered, leading to significant dynamic power. Moreover, prior approximate designs often overlook transistor sizing optimization, which limits their potential for power–delay efficiency. This article proposes a custom design and optimization framework for approximately 4-2 compressors at the structural and circuit levels, which effectively reduces glitches by balancing output delays. Based on the devised approximate 4-2 compressors, the constructed multipliers can then achieve significant reductions in the generation and propagation of spurious activities. In addition, to further reduce the dynamic power consumption, a delay-aware signal routing (DASR) strategy is introduced for interconnecting approximate compressors. The stability and efficiency of the proposed designs under varying conditions are verified by extensive simulations. The experimental results on HLMC 28-nm CMOS technology show that the approximate 4-2 compressors obtained by the proposed framework achieve 10.4%–52.1% power–delay product (PDP) reductions compared to existing approximate designs with the same accuracy, resulting in 5.20%–33.1% PDP improvements for multipliers. Moreover, the proposed optimization framework is generalizable to arbitrary approximate 4-2 compressor designs.

Matrix multiplication dominates the power consumption in compute-intensive applications such as deep neural networks (DNNs), spurring intensive investigations into power-efficient multiply-accumulate (MAC) units. Among the mainstream low-power design methodologies, voltage underscaling can achieve effective power savings yet induce timing errors that may lead to catastrophic accuracy loss. In this paper, we propose an error prediction and correction framework (denoted as EPIC) for arbitrary MAC unit under voltage underscaling, which predicts the timing errors and samples the correct output by using a delay-tunable clock. A prediction bits searching algorithm is proposed to enhance the prediction accuracy with low hardware cost, resulting in up to 100% accuracy. While preserving the accuracy, EPIC achieves up to 52% power savings over the corresponding MAC operating at nominal voltage. With transistor-level optimizations, EPIC incurs only 8% area and 1% power overheads, achieving 100% error correction under a voltage underscaling ratio of $\mathbf{0. 7 4}$. Compared to state-of-the-art error resilient circuit designs, EPIC consumes 60%-88% less area. Additionally, to achieve the accuracy performance of EPIC in error-resilient applications, we propose a simulation workflow involving precise timing features, enabling an accurate simulation of voltage underscaling MAC in large-scale applications. The experimental results show that, under voltage-underscaling, the MAC with EPIC consumes 11% less power than the one without EPIC, when a same accuracy as exact implementation is required in multi-layer perceptron (MLP).