The advent of heterogeneous integration (HI) places new demands on EDA tooling. Building large systems requires (1) methods for chiplet disaggregation that map the system to smaller chiplets, working in conjunction with system-technology co-optimization to determine the right design decisions that optimize computation and communication, together with the choice of substrate and chiplet technologies; (2) multiphysics and multiscale analyses that incorporate thermomechanical aspects into performance analysis, ranging from fast machine-learningdriven analyses in early stages to signoff-quality multiphysics-based analysis; (3) physical design techniques for placing and routing chiplets and embedded active/passive elements on and within the substrate, including the design of thermal and power delivery solutions; and (4) underlying infrastructure required to facilitate HI-based design, including the design and characterization of chiplet libraries and the establishment of data formats and standards. This paper overviews these issues and lays out a set of EDA needs for HI designs.

Power delivery is a significant bottleneck in 2.5D heterogeneously integrated (HI) systems. A key part of the solution lies in the use of voltage regulators that distribute power to the chiplets with low transmission losses, thus ensuring supply levels that meet design specifications. Early HI systems have used manual approaches for placement, but as systems grow more complex and employ heterogeneous chiplets with nonuniform power distributions, the solution becomes nontrivial, and automation is essential. This paper addresses the problem of voltage regulator selection and placement for early-stage power planning in HI systems under DC estimates of chiplet loads. It demonstrates an HI technology using an active silicon interposer with embedded switched-capacitor voltage regulators (SCVRs). The problem is formulated as a 0–1 mixed integer linear program (MILP) and determines the optimal number, location, and types of SCVRs. A key part of the solution is using a macromodeling approach to control the size of the MILP. Experimental results across four test cases—covering both homogeneous and heterogeneous chiplet configurations—demonstrate that the method can efficiently find optimal solutions. The tested scenarios span a wide range of power densities, from 0.8 to 4.0W/mm2, and include total load currents ranging from 800A to 1200A. In all cases, the method achieves high accuracy (average error below 1.7%) and completes the optimization within practical runtimes, ranging from 18.8 to 46.1 minutes.