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Xiangcan Xu

dblp:416/6913 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2026
0009-0006-2175-0750ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Software-defined and programmable networks · 100%
Software engineering, system software, and programming languages
2 papers
Operating systems · 64% Programming languages and type systems · 36%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Memory systems · 74% Processor architecture and microarchitecture · 26%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Software-defined and programmable networks › programmable data plane
in-network computation
1.012026
Rearchitecting Programmable Networks For In-Network Computing: From Hardware To Language · EuroSys 2026
Software-defined and programmable networks
programmable data plane
1.012026
Rearchitecting Programmable Networks For In-Network Computing: From Hardware To Language · EuroSys 2026
Programming languages and type systems
domain-specific languages
1.012026
Rearchitecting Programmable Networks For In-Network Computing: From Hardware To Language · EuroSys 2026
Operating systems › resource management
memory management
0.912025
CortenMM: Efficient Memory Management with Strong Correctness Guarantees · SOSP 2025
Operating systems › resource management › memory management
page table management
0.912025
CortenMM: Efficient Memory Management with Strong Correctness Guarantees · SOSP 2025
Memory systems
virtual memory management
0.912025
CortenMM: Efficient Memory Management with Strong Correctness Guarantees · SOSP 2025
Processor architecture and microarchitecture › special-purpose processor
network processor
0.312026
Rearchitecting Programmable Networks For In-Network Computing: From Hardware To Language · EuroSys 2026

Methods — techniques the papers use, named apart from their topics

operation-action table · 3.0hierarchical memory pool · 3.0concurrency bug analysis · 1.7
YearPublicationVenuePosition
2026 Rearchitecting Programmable Networks For In-Network Computing: From Hardware To Language
abstract
In-network computing (INC) offers orders-of-magnitude performance gains for various applications. However, the existing pipeline-based switch architecture, though well-suited for stateless packet forwarding, imposes three constraints on stateful INC applications: (i) control-plane table management, (ii) scarce memory resources under per-stage layout, and (iii) a strict memory access model. To address these constraints, this paper provides a full-stack solution, covering a programmable chipset Solar-NP, a programming language NPC, and a complete toolchain XuanWu. First, Solar-NP adopts a run-to-completion-based (RTC-based) architecture with three new hardware features: data-plane table management, a hierarchical memory pool, and built-in data structures with atomic access guarantees. Second, to fully exploit the hardware features, our language NPC introduces a new abstraction, namely operation-action table (OAT), that allows table manipulations in the data plane. Finally, our XuanWu toolchain provides various utility software covering the complete workflow of developing, testing, debugging, and deployment. To show the power of our solution, we implement three types of INC cases, including in-network control, in-network telemetry, and in-network storage. Experimental results demonstrate that our solution allows more operations to be offloaded and achieves higher performance than today's pipeline-based solutions.
Haifeng Sun 0002, Taixu Tian, Jinbo Sun, Jintao He, Qun Huang 0001, Luyou He, Xiangcan Xu, Junyi Guo, Yongqiang Yang
EuroSys11
2025 CortenMM: Efficient Memory Management with Strong Correctness Guarantees
abstract
Modern memory management systems suffer from poor performance and subtle concurrency bugs, slowing down applications while introducing security vulnerabilities. We observe that both issues stem from the conventional design of memory management systems with two levels of abstraction: a software-level abstraction (e.g., VMA trees in Linux) and a hardware-level abstraction (typically, page tables). This design increases portability but requires correctly and efficiently synchronizing two drastically different and complex data structures, which is generally challenging.
Junyang Zhang 0003, Xiangcan Xu, Yonghao Zou, Xinyi Wan 0001, Siyuan Wang 0026, Di Wang 0017, Hao Chen 0023, Lin Huang 0005, Shoumeng Yan, Yuval Tamir, Yingwei Luo, Xiaolin Wang 0001, Huashan Yu, Zhenlin Wang 0003, Hongliang Tian, Diyu Zhou
SOSP2