Demo Data from EDBT 2026 / reviewers in the wild / expert
Yipei Yan
dblp:416/8693
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2025
0009-0008-3904-3119ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Embedded and real-time systems · 56% Electronic design automation · 44% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
benchmark generation |
0.9 | 1 | 2025 | Automated Generation of Benchmarks for Falsification of STL Specifications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Embedded and real-time systems
cyber-physical systems |
0.9 | 1 | 2025 | Automated Generation of Benchmarks for Falsification of STL Specifications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Embedded and real-time systems › cyber-physical systems
signal temporal logic specification |
0.3 | 1 | 2025 | Automated Generation of Benchmarks for Falsification of STL Specifications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Methods — techniques the papers use, named apart from their topics
data-driven trace generation · 0.9LSTM · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Automated Generation of Benchmarks for Falsification of STL SpecificationsabstractFalsification, whose aim is to detect unsafe behaviors of cyber-physical systems (CPS) that violate signal temporal logic (STL) specifications, has been actively investigated in the past decade. Although numerous falsification approaches have been proposed, the falsification community suffers from a shortage of benchmarks that hinders a thorough assessment of those falsification approaches. In this article, we bridge this gap by proposing an automated approach for generating falsification benchmarks. Our approach is data-driven: first, we generate different time-variant traces (acting as system output traces) that satisfy a given STL specification, and we associate these with corresponding system input traces; then, we use these input and output traces to train an LSTM model that generalizes them. These models can serve as benchmarks for assessing falsification approaches against the given specification. In the experimental evaluation, we validate the generated models by measuring their ability to differentiate the performance of different falsification approaches. Our generated models expose strengths and weaknesses of all the considered falsification approaches, which was not achieved by benchmarks currently used in the falsification community. These results demonstrate the usefulness of our approach and can potentially push forward subsequent research in falsification. Yipei Yan, Deyun Lyu, Zhenya Zhang 0001, Paolo Arcaini, Jianjun Zhao 0001 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |