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Jinhong Mo

dblp:419/1547 · DBLP profile ↗
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1ranked-venue papers
1as first author
1since 2021 · last 2025
0009-0006-5448-1526ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Storage systems · 67% Hardware reliability and fault tolerance · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance
error correction
0.912025
SC-GC-LDPC for nand Flash Memory: Construction and Decoding · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Storage systems › flash and SSD
flash memory
0.912025
SC-GC-LDPC for nand Flash Memory: Construction and Decoding · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Storage systems › flash and SSD › flash memory
LDPC decoding
0.912025
SC-GC-LDPC for nand Flash Memory: Construction and Decoding · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025

Methods — techniques the papers use, named apart from their topics

two-level decoding · 0.9layered sum-product algorithm · 0.9layered normalized min-sum · 0.9
YearPublicationVenuePosition
2025 SC-GC-LDPC for nand Flash Memory: Construction and Decoding
abstract
With the continuous improvement of data memory density, as the common solution for error correction of NAND flash, the low-density-parity-check (LDPC) code faces more challenges, such as the increasing code length requirements, the worse raw bit error rates (RBER), and the frequently varied channels. In this paper, a new (37536,33672) spatially coupled and globally coupled LDPC (SC-GC-LDPC) code is constructed to address the above challenge, which outperforms the traditional globally coupled LDPC (GC-LDPC) code with the gaps of 0.065 dB and 0.08 dB by exploiting the layered sum-product algorithm (SPA) and the layered normalized min-sum (NMS) algorithm, respectively. In the flash channel, the SC-GC-LDPC code also shows superior error correction performance than the conventional GC-LDPC codes with 25% improvement. Due to its special structure of the check matrix, an improved two-level decoding algorithm (ITLA) and an improved two-phase decoding algorithm (ITPA) are proposed in this paper. Specifically, the algorithms exploit the adjacent subcodes to correct the faulty ones, which reduces the number of check-node-updating (CNU). For the case of single subcode errors, the simulation results show that the number of CNU is reduced by ranging from 6.64% to 31.14% by applying our proposed algorithms, leading to significant improvement of throughput. Compared with the conventional algorithms, the ITLA and ITPA only show slight performance loss. Moreover, ITPA also provides high flexibility of decoding in the NAND flash memory, which can achieve the balance between the error-correction performance and the throughput.
Jinhong Mo, Xiongfei Zhai, Yi Fang 0005, Guojun Han
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1