Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Lirong Lai

dblp:419/8766 · DBLP profile ↗
← Back
2ranked-venue papers
0as first author
2since 2021 · last 2026
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Software-defined and programmable networks · 77% Network optimization and economics · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Software-defined and programmable networks › programmable data plane
programmable switch
1.012026
Net-P4ct: Enhanced WAN Bandwidth Fair Sharing Using P4 Programmable Switches · NSDI 2026
Network optimization and economics › resource allocation
bandwidth allocation
0.312026
Net-P4ct: Enhanced WAN Bandwidth Fair Sharing Using P4 Programmable Switches · NSDI 2026
YearPublicationVenuePosition
2026 Net-P4ct: Enhanced WAN Bandwidth Fair Sharing Using P4 Programmable Switches
Mingwei Cui, Yihan Zou, Yihang Miao, Suhan Jiang, Damu Ding, Lirong Lai, Shengyuan He, Anjian Chen, Jiaming Shi, Junjie Wan, Yandong Duan, Ruomin Fang, Yongping Tang, Qiao Kang, Guangrui Wu, Xiyun Xu
NSDI7
2026 Gryphon: Scaling Hyperscale Multi-Tenant Gateways Beyond the Petabit-Era via DPU-Augmented Hierarchical Co-Offloading
abstract
At ByteDance, cloud gateway clusters orchestrate petabit-scale aggregate traffic. Traditional ASIC-only gateways fail to meet these escalating demands due to severe on-chip resource constraints and limited programmable flexibility, while pure software solutions or alternatives like disaggregated SmartNICs struggle to match terabit-scale line-rate throughput. To bridge this gap, we present Gryphon, a hyperscale cloud gateway built on a hybrid architecture that integrates DPUs directly into the switching ASIC's forwarding path. This design resolves the fundamental tension between capacity and speed, expanding table scale by up to 1000× and augmenting programmability, while sustaining 1.6 Tbps line-rate throughput at a cost of only ~8 μs in additional average latency. To manage this hardware heterogeneity, we introduce Hierarchical Co-Offloading (HLCO) in the data plane, achieving >99.9% fast path hit rate, while retaining software fallback for complex operations. In the control plane, we develop an abstraction layer (P4Bridge) that decouples hardware specifics from policy configuration. Gryphon has been operating at production scale for over a year, deployed on hundreds of nodes across multiple Availability Zones. We also share production measurements and operational experiences that serve as the first hyperscale-proven guidelines for next-generation DPU-augmented cloud gateways.
Yuemeng Xu, Jiarui Guo, Mingwei Cui, Qiuheng Yin, Peng He 0003, Chenmin Sun, Yangyujia Wang, Daxiang Kang, Lirong Lai, Zhuochen Fan, Tong Yang 0003
SIGCOMM13