Hardware Trojan detection through side-channel analysis in physical chips is very challenging due to the presence of manufacturing process variations. Numerous Trojan detection approaches are in the literature. However, most of them are limited to netlist level identification and unable to explain the process variation issue in post-silicon chips. In this work, we propose a new detection technique with delay side-channel analysis that can detect all types of Trojans under the presence of high process variations. The technique is termed as zero delay deviation (ZDD) that is capable of diminishing the effect of all variations and other noise sources to identify the Trojan presence in chips. The ZDD approach is achieved by 1) a novel equal-delay circuit partitioning, 2) placing a highly secured camouflaged ring oscillator PUF per partition to generate equal-delay challenge-response pairs that delivers the knowledge of variation trends, 3) generating Identical Delay (ID) neighboring pairs for both, partitions and PUF designs that ensure nullifying the variation effects upon comparing them. The ZDD is examined through an intra-referencing of ID pairs with PUF-RD pairs in ISCAS’85 and 89 benchmarks. 10,000 virtual chips are generated by Monte Carlo simulation considering all physical characteristics of a real chip. Results demonstrate that the proposed approach can successfully detect Trojans even if it consists of a single gate. A comparison to the state-of-the-art shows the method superiority over others.

A hardware Trojan (HT) denotes the malicious addition or modification of circuit elements. The purpose of this work is to improve the HT detection sensitivity in ICs using power side-channel analysis. This paper presents three detection techniques in power based side-channel analysis by increasing Trojan-to-circuit power consumption and reducing the variation effect in the detection threshold. Incorporating the three proposed methods has demonstrated that a realistic fine-grain circuit partitioning and an improved pattern set to increase HT activation chances can magnify Trojan detectability.

High detection sensitivity in the presence of process variation is a key challenge for hardware Trojan detection through side channel analysis. In this work, we present an efficient Trojan detection approach in the presence of elevated process variations. The detection sensitivity is sharpened by 1) comparing power levels from neighboring regions within the same chip so that the two measured values exhibit a common trend in terms of process variation, and 2) generating test patterns that toggle each cell multiple times to increase Trojan activation probability. Detection sensitivity is analyzed and its effectiveness demonstrated by means of RPD (relative power difference). We evaluate our approach on ISCAS'89 and ITC'99 benchmarks and the AES-128 circuit for both combinational and sequential type Trojans. High detection sensitivity is demonstrated by analysis on RPD under a variety of process variation levels and experiments for Trojan inserted circuits.

The sensitive identification and detection of hardware Trojans in ICs without a golden reference constitutes a key challenge. Traditional circuit partitioning and side-channel analysis techniques fall short of perfect sensitivity and accuracy and rely on golden references. In this work, a novel layout-aware clock tree driven circuit partitioning is coupled with an algorithm that selects transition delay fault test patterns that will deliver equal power on partitions. The circuit partitioning through the clock tree results in minimal hardware additions that can be effected through ECO. The selection of pairs of power uniform small regions results in reduction of inter-die variation effects, thus delivering increased detection sensitivity. The comparison for equal power of numerous pairs thoroughly perturbs the circuit under various activation conditions, resulting in elevated sensitivity and accuracy while obviating the need for reliance on Golden ICs. We evaluate our approach on ISCAS89 and ITC benchmarks and AES circuits for both combinational and sequential type Trojans. Experimental results show that our approach can effectively detect Trojans with ratios to circuit area as low as 0.023%.