NISQ (Noisy, Intermediate-Scale Quantum) computing requires error mitigation to achieve meaningful computation. Our compilation tool development focuses on the fact that the error rates of individual qubits are not equal, with a goal of maximizing the success probability of real-world subroutines such as an adder circuit. We begin by establishing a metric for choosing among possible paths and circuit alternatives for executing gates between variables placed far apart within the processor, and test our approach on two IBM 20-qubit systems named Tokyo and Poughkeepsie. We find that a single-number metric describing the fidelity of individual gates is a useful but imperfect guide. Our compiler uses this subsystem and maps complete circuits onto the machine using a beam search-based heuristic that will scale as processor and program sizes grow. To evaluate the whole compilation process, we compiled and executed adder circuits, then calculated the Kullback–Leibler divergence (KL-divergence, a measure of the distance between two probability distributions). For a circuit within the capabilities of the hardware, our compilation increases estimated success probability and reduces KL-divergence relative to an error-oblivious placement.

Quantum Teleportation is the key communication functionality of the Quantum Internet, allowing the “transmission” of qubits without the physical transfer of the particle storing the qubit. Quantum teleportation is facilitated by the action of quantum entanglement, a somewhat counter-intuitive physical phenomenon with no direct counterpart in the classical word. As a consequence, the very concept of the classical communication system model has to be redesigned to account for the peculiarities of quantum teleportation. This re-design is a crucial prerequisite for constructing any effective quantum communication protocol. The aim of this manuscript is to shed light on this key concept, with the objective of allowing the reader: i) to appreciate the fundamental differences between the transmission of classical information versus the teleportation of quantum information; ii) to understand the communications functionalities underlying quantum teleportation, and to grasp the challenges in the design and practical employment of these functionalities; iii) to acknowledge that quantum information is subject to the deleterious effects of a noise process termed as quantum decoherence. This imperfection has no direct counterpart in the classical world; iv) to recognize how to contribute to the design and employment of the Quantum Internet.

Quantum computers promise substantial speedups over conventional machines for many practical applications. While considered "dreams of the future" for a long time, first quantum computers are available now which can be utilized by anyone. A leading force within this development is IBM Research which launched the IBM Q Experience - the first industrial initiative to build universal quantum computers and make them accessible to a broad audience through cloud access. Along this initiative, the tool Qiskit has been launched which enables researchers, teachers, developers, and general enthusiasts to write corresponding code and to run experiments on those machines. At the same time, this provides an ideal playground for the design automation community which - through Qiskit - can deploy improved solutions e.g. on designing and realizing quantum applications. This special session summary aims to provide an introduction into Qiskit and is showcasing selected success stories on how to work with and develop for it. In addition to that, it provides corresponding references to further readings in terms of tutorials and scientific papers as well as links to publicly available implementations for Qiskit extensions.

The optimal design of a fault-tolerant quantum computer involves finding an appropriate balance between the burden of large-scale integration of noisy components and the load of improving the reliability of hardware technology. This balance can be evaluated by quantitatively modeling the execution of quantum logic operations on a realistic quantum hardware containing limited computational resources. In this work, we report a complete performance simulation software tool capable of (1) searching the hardware design space by varying resource architecture and technology parameters, (2) synthesizing and scheduling a fault-tolerant quantum algorithm within the hardware constraints, (3) quantifying the performance metrics such as the execution time and the failure probability of the algorithm, and (4) analyzing the breakdown of these metrics to highlight the performance bottlenecks and visualizing resource utilization to evaluate the adequacy of the chosen design. Using this tool, we investigate a vast design space for implementing key building blocks of Shor’s algorithm to factor a 1,024-bit number with a baseline budget of 1.5 million qubits. We show that a trapped-ion quantum computer designed with twice as many qubits and one-tenth of the baseline infidelity of the communication channel can factor a 2,048-bit integer in less than 5 months.

Blind quantum computation is an appealing use of quantum information technology because it can conceal both the client's data and the algorithm itself from the server. However, problems need to be solved in the practical use of blind quantum computation and fault-tolerance is a major challenge. Broadbent et al. proposed running error correction over blind quantum computation, and Morimae and Fujii proposed using fault-tolerant entangled qubits as the resource for blind quantum computation. Both approaches impose severe demands on the teleportation channel, the former requiring unrealistic data rates and the latter near-perfect fidelity. To extend the application range of blind quantum computation, we suggest that Alice send input qubits encoded with error correction code instead of single input qubits. Two fault-tolerant protocols are presented and we showed the trade-off of the computational overhead using the ten-bit quantum carry-lookahead adder as an example. Though these two fault-tolerant protocols require the client to have more quantum computing ability than using approaches from prior work, they provide better fault-tolerance when the client and the server are connected by realistic quantum repeater networks.

Reversible logic has applications in low-power computing and quantum computing. However, there are few existing designs for reversible floating-point adders and none suitable for quantum computation. In this article, we propose a resource-efficient reversible floating-point adder, suitable for binary quantum computation, improving the design of Nachtigal et al. [2011]. Our work focuses on improving the reversible designs of the alignment unit and the normalization unit, which are the most expensive parts. By changing a few elements of the existing algorithm, including the circuit designs of the RLZC (reversible leading zero counter) and converter, we have reduced the cost by about 68%. We also propose quantum designs adapted to use gates from fault-tolerant libraries. The KQ for our fault-tolerant design is almost 60 times as expensive as for a 32-bit fixed-point addition. We note that the floating-point representation makes in-place, truly reversible arithmetic impossible, requiring us to retain both inputs, which limits the sustainability of its use for quantum computation.

We propose the Floating Ground Architecture (FGA) for network mobility and ad hoc network convergence. Various factors, including excessive dependence on intelligence in the fixed network, result in the Internet having a de facto logical boundary one hop from the fixed network. To reduce these dependencies, FGA introduces a new logical layer, called Floating Ground, between the fixed network infrastructure and the mobile network, aiming to bridge these different types of network systems. Thanks to the effect of this buffer layer, the architecture: 1) optimizes routes in a deeply nested mobile router arrangement, 2) simplifies mobility event handling under frequent movement of the nodes, and 3) transparently introduces additional functionality with no additional intelligence on the infrastructure side. Through evaluation of our proposed architecture using an actual software implementation running via Direct Code Execution simulation, optimized routes are confirmed with three possible mobility scenarios, demonstrating the handoff duration is dramatically reduced in the short-distance movement scenario, which happens in 78.4%, at maximum, of the handoff events under actual taxi cabs movement in real world. Qualitative analysis of FGA shows it minimizes modification of the network components and existing standardized protocols, and is therefore more suitable for self-organized, distributed network extension than competitive approaches.

Quantum algorithms can be written down in several forms, one of the most common is the quantum circuit representation using discrete gates. The challenge in assessing the computational cost then becomes counting those gates, with realistic costs assigned to each gate. Moreover, interacting pairs of qubits inside most quantum computers will require moving qubits. In many architectures, this will involve cellular automaton-like swapping of qubits. In general, the depth will be described in number of quantum error correction (QEC) cycles, while the total cost will be space-time ``volume'' consisting of the number of qubits involved over that set of QEC cycles. This implies that accurate estimates can be made only in the context of a particular architecture and error correction mechanism.

In this work, we propose an adder for the 2-Dimensional Nearest-Neighbor, Two-Qubit gate, Concurrent (2D NTC) architecture, designed to match the architectural constraints of many quantum computing technologies. The chosen architecture allows the layout of logical qubits in two dimensions with √ n columns where each column has √ n qubits and the concurrent execution of one- and two-qubit gates with nearest-neighbor interaction only. The proposed adder works in three phases. In the first phase, the first column generates the summation output and the other columns do the carry-lookahead operations. In the second phase, these intermediate values are propagated from column to column, preparing for computation of the final carry for each register position. In the last phase, each column, except the first one, generates the summation output using this column-level carry. The depth and the number of qubits of the proposed adder are Θ(√ n ) and O(n) , respectively. The proposed adder executes faster than the adders designed for the 1D NTC architecture when the length of the input registers n is larger than 51.

We investigate the theoretical limits of the effect of the quantum interaction distance on the speed of exact quantum addition circuits. For this study, we exploit graph embedding for quantum circuit analysis. We study a logical mapping of qubits and gates of any Ω (log n )-depth quantum adder circuit for two n -qubit registers onto a practical architecture, which limits interaction distance to the nearest neighbors only and supports only one- and two-qubit logical gates. Unfortunately, on the chosen k -dimensional practical architecture, we prove that the depth lower bound of any exact quantum addition circuits is no longer Ω (log n ), but Ω ( k √ n ). This result, the first application of graph embedding to quantum circuits and devices, provides a new tool for compiler development, emphasizes the impact of quantum computer architecture on performance, and acts as a cautionary note when evaluating the time performance of quantum algorithms.

In hop-by-hop networks, provision of multipath routes for all nodes can improve fault tolerance and performance. In this paper we study the multipath route calculation by constructing a directed acyclic graph (DAG) which includes all edges in the network. We define new DAG construction problems with the objectives of 1) maximizing the minimum connectivity, 2) maximizing the minimum max-flow, and 3) maximizing the minimum max-flow as an extension of shortest path routing. A family of new algorithms called Maximum Alternative Routing Algorithms (MARAs) is described, proven formally to solve the problems optimally, and contrasted with existing multipath algorithms. MARAs are evaluated for the number of paths, the length of paths, the computational complexity, and the computation time, using simulations based on several real Internet Autonomous System (AS) network topologies. We show that MARAs run in sub-second times on moderate-speed processors and achieve a significant increase in the number of paths compared to existing multipath routing algorithms. These results should help further the process of deploying multipath routing in real-world networks.

We evaluate the performance of quantum arithmetic algorithms run on a distributed quantum computer (a quantum multicomputer). We vary the node capacity and I/O capabilities, and the network topology. The tradeoff of choosing between gates executed remotely, through “teleported gates” on entangled pairs of qubits (telegate), versus exchanging the relevant qubits via quantum teleportation, then executing the algorithm using local gates (teledata), is examined. We show that the teledata approach performs better, and that carry-ripple adders perform well when the teleportation block is decomposed so that the key quantum operations can be parallelized. A node size of only a few logical qubits performs adequately provided that the nodes have two transceiver qubits. A linear network topology performs acceptably for a broad range of system sizes and performance parameters. We therefore recommend pursuing small, high-I/O bandwidth nodes and a simple network. Such a machine will run Shor's algorithm for factoring large numbers efficiently.

Distributed quantum computation requires quantum operations that act over a distance on error correction-encoded states of logical qubits, such as the transfer of qubits via teleportation. We evaluate the performance of several quantum error correction (QEC) codes and find that teleportation failure rates of one percent or more are tolerable when two levels of the [[23, 1, 7]] code are used. We present an analysis of performing QEC on QEC-encoded states that span two quantum computers, including the creation of distributed logical zeros. The transfer of the individual qubits of a logical state may be multiplexed in time or space, moving serially across a single link or in parallel across multiple links. We show that the performance and reliability penalty for using serial links is small for a broad range of physical parameters, making serial links preferable for a large, distributed quantum multicomputer when engineering difficulties are considered. Such a multicomputer will be able to factor a 1,024-bit number using Shor's algorithm with a high probability of success.

We evaluate the performance of quantum arithmetic algorithms run on a distributed quantum computer (a quantum multicomputer). We vary the node capacity and I/O capabilities, and the network topology. The tradeoff of choosing between gates executed remotely, through "tele-ported gates" on entangled pairs of qubits (telegate), versus exchanging the relevant qubits via quantum teleportation, then executing the algorithm using local gates (tele-data), is examined. We show that the teledata approach performs better, and that carry-ripple adders perform well when the teleportation block is decomposed so that the key quantum operations can be parallelized. A node size of only a few logical qubits performs adequately provided that the nodes have two transceiver qubits. A linear network topology performs acceptably for a broad range of system sizes and performance parameters. We therefore recommend pursuing small, high-I/O bandwidth nodes and a simple network. Such a machine will run Shor's algorithm for factoring large numbers efficiently

In this article we present a classification scheme for quantum computing technologies that is based on the characteristics most relevant to computer systems architecture. The engineering trade-offs of execution speed, decoherence of the quantum states, and size of systems are described. Concurrency, storage capacity, and interconnection network topology influence algorithmic efficiency, while quantum error correction and necessary quantum state measurement are the ultimate drivers of logical clock speed. We discuss several proposed technologies. Finally, we use our taxonomy to explore architectural implications for common arithmetic circuits, examine the implementation of quantum error correction, and discuss cluster-state quantum computation.

In this paper we describe the implementation of VISA, our Virtual Internet SCSI Adapter. VISA was built to evaluate the performance impact on the host operating system of using IP to communicate with peripherals, especially storage devices. We have built and benchmarked file systems on VISA-attached emulated disk drives using UDP/IP. By using IP, we expect to take advantage of its scaling characteristics and support for heterogeneous media to build large, long-lived systems. Detailed file system and network CPU utilization and performance data indicate that it is possible for UDP/IP to reach more than 80% of SCSI's maximum throughput without the use of network coprocessors. We conclude that IP is a viable alternative to special-purpose storage network protocols, and presents numerous advantages.