Memory vulnerabilities are a major threat to many computing systems. To effectively thwart spatial and temporal memory vulnerabilities, full logical memory safety is required. However, current mitigation techniques for memory safety are either too expensive or trade security against efficiency. One promising attempt to detect memory safety vulnerabilities in hardware is memory coloring, a security policy deployed on top of tagged memory architectures. However, due to the memory storage and bandwidth overhead of large tags, commodity tagged memory architectures usually only provide small tag sizes, thus limiting their use for security applications.

This paper describes the system architecture, design methodology and subsequent FPGA mapping of a millimeter wave digital baseband for wireless communication in the 60GHz spectral band. The baseband is designed to be compliant with the 802.11ad Single Carrier and Control PHY draft specifications and supports a data rate of 2.5Gbps at the physical layer. The demanding throughput and latency requirements are achieved with a parallel implementation. However, due to limited capacity of the FPGAs present in our prototype platform and complex partitioning requirements, only a scaled down version of the full single carrier baseband that operates at 1/10th the throughput of the specification could be mapped. A minimal real-time hardware MAC was also incorporated and coupled with a 60GHz RF beam-forming front-end to demonstrate file transfer between two independent FPGA prototyping systems. A system throughput of 59Mbps was achieved at the application layer using π/2 QPSK modulation with a 13/16 LDPC code rate.

Power consumption of digital baseband processing of a wireless receiver can be reduced by operating the circuits at a reduced voltage where setup timing errors occur occasionally in a controlled way. One of the challenges is then to estimate the BER of the receiver and to create a control loop that controls the voltage such that the estimated BER is within the specifications of the system. The paper describes two mechanisms to realize such a control loop. The first one uses parity-based error detection; the second one is based on the application of forward error correction in the system. Both mechanisms have been modeled in an industrial low power receiver design that includes a model for setup timing error injection. Simulation results show that the control loops are able to accurately control the voltage to the lowest possible level such that the BER stays within the specified constraints.

Multicore architectures provide scalable performance with a lower hardware design effort than single core processors. Our article presents a design methodology and an embedded multicore architecture, focusing on reducing the software design complexity and boosting the performance density. First, we analyze characteristics of the Task-Level Parallelism in modern multimedia workloads. These characteristics are used to formulate requirements for the programming model. Then we translate the programming model requirements to an architecture specification, including a novel low-complexity implementation of cache coherence and a hardware synchronization unit. Our evaluation demonstrates that the novel coherence mechanism substantially simplifies hardware design, while reducing the performance by less than 18% relative to a complex snooping technique. Compared to a single processor core, the multicores have already proven to be more area- and energy-efficient. However, the multicore architectures in embedded systems still compete with highly efficient function-specific hardware accelerators. In this article we identify five architectural methods to boost performance density of multicores; microarchitectural downscaling, asymmetric multicore architectures, multithreading, generic accelerators, and conjoining. Then, we present a novel methodology to explore multicore design spaces, including the architectural methods improving the performance density. The methodology is based on a complex formula computing performances of heterogeneous multicore systems. Using this design space exploration methodology for HD and QuadHD H.264 video decoding, we estimate that the required areas of multicores in CMOS 45 nm are 2.5 mm 2 and 8.6 mm 2 , respectively. These results suggest that heterogeneous multicores are cost-effective for embedded applications and can provide a good programmability support.

We propose a smart compilation chain in which the compiler is no longer limited by a pre-defined instruction set, but can generate application-specific custom instructions and synthesise them in Field-Programmable Logic. We also present a RISC micro-architecture enhanced by a CPLD-based Reconfigurable Functional Unit (RFU) which supports our compiler approach. The main difference between our smart compiler and similar methods is the ability to encode multiple custom instructions in a single RFU configuration, cross-minimising the logic among them. The objective is to reduce (or eliminate) the reconfiguration overhead and optimise the utilisation of resources. The CPLD core that implements the RFU is based on the Philips XPLA2 architecture. We discuss the advantages of using the XPLA2 instead of conventional FPGAs. Application examples are also presented, which show that our RFU-extended CPU can achieve speed-ups of more than 40% for encryption algorithms, when compared to the standard CPU core alone.

This paper describes a system for compressed code generation. The code of applications is partioned into time-critical and non-time-critical code. Critical code is compiled to native code, and non-critical code is compiled to a very dense virtual instruction set which is executed on a highly optimized interpreter. The system employs dictionary-based compression by means of superinstructions which correspond to patterns of frequently used base instructions. The code compression system is designed for the Philips TriMedia VLIW processor. The interpreter is pipelined to achieve a high interpretation speed. The pipeline consists of three stages: fetch, decode, and execute. While one instruction is being executed, the next instruction is decoded, and the next one after that is fetched from memory. On a TriMedia VLIW with a load latency of three cycles and a jump latency of four cycles, the interpreter achieves a peak performance of four cycles per instruction and a sustained performance of 6.27 cycles per instruction. Experiments are described that demonstrate the compression quality of the system and the execution speed of the pipelined interpreter; these were found to be about five times more compact than native TriMedia code and a slowdown of about eight times, respectively. Copyright © 1999 John Wiley & Sons, Ltd.

This paper presents an overview of the activities carried out within the ESPRIT project OCEANS whose objective is to investigate and develop advanced compiler infrastructure for embedded VLIW processors. This combines high and low-level optimisation approaches within an iterative framework for compilation. These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Exploitation of large amounts of instruction level parallelism requires a large amount of connectivity between the shared register file and the function units; this connectivity is expensive and increases the cycle time. This paper shows that the new class of transport triggered architectures requires fewer ports on the shared register file than traditional operation triggered architectures. This is achieved by programming data-transports instead of operations. Experiments with our extended basic block scheduler have shown that the reduction of the required number of register file ports is substantial. The average requirement for scalar applications is 0.50 read and 0.35 write ports per operation instead of 2 read and 1 write ports. Due to this reduction it is possible to execute 2 operations per cycle with a two-ported register file and 3.6 operations per cycle with a six-ported register file.

Article Software pipelining for transport-triggered architectures Share on Authors: Jan Hoogerbrugge Delft University of Technology, Department of Electrical Engineering, Section Computer Architecture and Digital Systems Delft University of Technology, Department of Electrical Engineering, Section Computer Architecture and Digital SystemsView Profile , Henk Corporaal Delft University of Technology, Department of Electrical Engineering, Section Computer Architecture and Digital Systems Delft University of Technology, Department of Electrical Engineering, Section Computer Architecture and Digital SystemsView Profile , Hans Mulder Delft University of Technology, Department of Electrical Engineering, Section Computer Architecture and Digital Systems Delft University of Technology, Department of Electrical Engineering, Section Computer Architecture and Digital SystemsView Profile Authors Info & Claims MICRO 24: Proceedings of the 24th annual international symposium on MicroarchitectureSeptember 1991 Pages 74–81https://doi.org/10.1145/123465.123479Online:01 September 1991Publication History 12citation319DownloadsMetricsTotal Citations12Total Downloads319Last 12 Months4Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access