Demo Data from EDBT 2026 / reviewers in the wild / expert
Iksoo Pyo
dblp:42/1711
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1997
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 95% Processor architecture and microarchitecture · 5% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.0 | 1 | 1996 | Constructing Lower and Upper Bounded Delay Routing Trees Using Linear Programming · DAC 1996 |
Electronic design automation › physical design › routing
routing tree construction |
0.0 | 1 | 1996 | Constructing Lower and Upper Bounded Delay Routing Trees Using Linear Programming · DAC 1996 |
Electronic design automation › physical design › routing
timing-driven routing |
0.0 | 1 | 1996 | Constructing Lower and Upper Bounded Delay Routing Trees Using Linear Programming · DAC 1996 |
Processor architecture and microarchitecture
microprocessor design |
0.0 | 1 | 1992 | Application-Driven Design Automation for Microprocessor Design · DAC 1992 |
Methods — techniques the papers use, named apart from their topics
linear programming · 0.0application-driven design automation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1997 | Constructing minimal spanning/Steiner trees with bounded path length
Jaewon Oh, Iksoo Pyo, Massoud Pedram |
Integr. | 2 |
| 1996 | Constructing Lower and Upper Bounded Delay Routing Trees Using Linear ProgrammingabstractArticle Constructing lower and upper bounded delay routing trees using linear programming Share on Authors: Jaewon Oh University of Southern California, Department of Electrical Engineering, Los Angeles, CA University of Southern California, Department of Electrical Engineering, Los Angeles, CAView Profile , Iksoo Pyo Intel Corporation, JF1-61, Hillsboro, OR Intel Corporation, JF1-61, Hillsboro, ORView Profile , Massoud Pedram University of Southern California, Department of Electrical Engineering, Los Angeles, CA University of Southern California, Department of Electrical Engineering, Los Angeles, CAView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 401–404https://doi.org/10.1145/240518.240595Online:01 June 1996Publication History 7citation253DownloadsMetricsTotal Citations7Total Downloads253Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access Jaewon Oh, Iksoo Pyo, Massoud Pedram |
DAC | 2 |
| 1992 | Application-Driven Design Automation for Microprocessor Design
Iksoo Pyo, Ching-Long Su, Ing-Jer Huang, Kuo-Rueih Pan, Yong-Seon Koh, Chi-Ying Tsui, Hsu-Tsun Chen, Gino Cheng, Shihming Liu, Shiqun Wu, Alvin M. Despain |
DAC | 1 |