In this paper the technoeconomical benefits in the use of Ensemble of Regression Trees (ERT) Machine Learning method are explored for fish shape alignment. Various ERT models are trained on low contrast blur images of open water Mediterranean fish species. Shape alignment can be used to estimate morphological features (length, weight) and species variety. Moreover, shape malformations and color analysis of fish parts located by certain shape landmarks can also be used to assess freshness or fish health. Shape alignment based on 26 landmarks has been performed with a relative mean average error (MAE) of less than 3% and fish length estimation with MAE$<2 \%$. Hardware acceleration with reconfigurable hardware can be applied in some of the trained ERT models to perform a single fish shape alignment in less than 15 ms.

Indoor localization is a critical component of various applications, including assisted living, personnel monitoring, and asset tracking. Traditional localization methods relying on specialized sensors such as LiDAR, ultrasound, and 3D cameras offer high precision but suffer from high costs and limited interoperability. To address these challenges, this paper explores the Integrated Sensing and Communication (ISAC) paradigm, leveraging signal-based modalities focusing on received signal strength indication (RSSI). These measurements, inherently embedded in wireless communication packets, enable cost-effective and vendor-agnostic localization without the need for additional hardware. However, practical deployment remains challenging due to signal degradation from obstacles, multipath effects, and reflections. This paper presents an end-to-end localization framework utilizing COTS IoT devices and advanced RSSI processing techniques to enhance measurement reliability. By integrating filtering mechanisms and machine learning models, the proposed solution improves distance estimation, categorizes line-of-sight (LoS) and non-line-of-sight (NLoS) conditions, and enhances localization accuracy. Additionally, an open and extendable edge-to-cloud infrastructure supports scalability and real-time processing. Experimental evaluation demonstrate the effectiveness of this approach in various aspects such as increase of RSSI reliability (increase of up to 82 % regarding standard deviation, drastic reduction of outliers' detection and fluctuation of more than 90 % to distances up to 2 m), accurate LoS-NLoS classification up to 99 % and overall localization increased accuracy more than 83 %.

The safe and secure implementation of increasingly complex features is a major challenge in the development of autonomous and distributed embedded systems. Automated design-time procedures that guarantee the fulfillment of critical system properties are a promising approach to tackle this challenge. In the European project XANDAR, which took place from 2021 to 2023, eight partners developed an X-by-Construction (XbC) design framework to support developers in the creation of embedded software systems with certain safety, security, and real-time properties. The design framework combines a model-based toolchain with a hypervisor-based runtime architecture. It targets modern high-performance hardware, facilitates the integration of machine learning applications, and employs a library of trusted safety and security patterns to reduce the implementation and verification effort. This paper describes the concepts developed during the project, the prototypical implementation of the design framework, and its application in both an automotive and an avionics use case.

Realizing desired properties “by construction” is a highly appealing goal in the design of safety-critical embedded systems. As verification and validation tasks in this domain are often both challenging and time-consuming, the by-construction paradigm is a promising solution to increase design productivity and reduce design errors. In the XANDAR project, partners from industry and academia develop a toolchain that will advance current development processes by employing a modelbased X-by-Construction (XbC) approach. XANDAR defines a development process, metamodel extensions, a library of safety and security patterns, and investigates many further techniques for design automation, verification, and validation. The developed toolchain will use a hypervisor-based platform, targeting future centralized, AI-capable high-performance embedded processing systems. It is co-developed and validated in both an avionics use case for situation perception and pilot assistance as well as an automotive use case for autonomous driving.

Due to the incorporation of heterogeneous cores in modern multi-core systems, the exploitation of their full potential strongly depends on the proper mapping of an application to the platform. This work presents an approach to map static applications on heterogeneous platforms minimizing their makespan based on the Benders decomposition principle combined with an Integer Linear Programming (ILP) model. The proposed approach adopts a three-stage decomposition scheme, finding permutations of infeasible solutions to generate multiple cuts in every iteration. The first stage deals with the assignment of the tasks to the cores and the last one with their scheduling, whereas the second stage propagates new bounds based on the current assignment and provides an explanation of the infeasibility in the form of subsets of assignment variables. Based on that, other infeasible combinations are computed by checking their permutations and more Benders cuts are produced. The proposed method is compared with a two-stage decomposition approach and an ILP model and exhibits better performance in terms of solution time and number solved instances to optimality.

The integration of connected and autonomous technologies in safety-critical and cyber-physical systems offers great potential in the vital application domains of transportation, manufacturing and aerospace. These technological advancements are necessary to meet the increasing demand for intelligent services, as they open doors to new business models by analysing and sharing the generated data. However, where this sharing of mix-critical data and broader connectivity brings opportunities, it simultaneously presents serious cybersecurity and safety risks due to the cyber-physical nature of these systems. Hence, delivering these intelligent services securely, safely, and reliably to its consumers is a complex engineering and design problem. One of the ways to approach this engineering problem is to consider both system functional and non-functional properties (safety, security, reliability) and systematically integrate them across system design and operational life cycle. The XANDAR project investigates this approach and aims to develop holistic software design methods and architectures for safety-critical and cyber-physical systems that guarantee functional and non-functional properties “byconstruction”. This paper focuses on the non-functional aspects of the project and discusses the preliminary work. by presenting the core cybersecurity principles and uses them as a baseline to propose a holistic cybersecurity engineering process. The tasks of the proposed cybersecurity engineering process are also map onto relevant clauses of ISO 21434. In future, proposed work will be integrated into the XANDAR software toolchain and validated for an avionics situation perception pilot assistance and automotive autonomous driving use cases.

The 2D facial landmark alignment method, implemented in C++ in the open source libraries DLIB and Deformable Shape Tracking (DEST), is used in several applications such as driver drowsiness detection. The most challenging of these applications require fast video frame processing. Therefore, the alignment of the facial landmarks in a single video frame has to be performed with the minimum possible latency without precision loss. In this paper, the DEST implementation of the face alignment method that is based on regression trees is heavily restructured to reduce latency. The resulting face alignment predictor is implemented in C. The elimination of multiple nested routine calls, excessive argument copying, type conversions and integrity checks lead to a software implementation that is 240 times faster than the one provided in the DEST library. Moreover, the structure of the new face alignment predictor is appropriate for hardware implementation on a Field Programmable Gate Array (FPGA) for further acceleration1.

The next generation of networked embedded systems (ES) necessitates rapid prototyping and high performance while maintaining key qualities like trustworthiness and safety. However, development of safety-critical ES suffers from complex software (SW) toolchains and engineering processes. Moreover, the current trend in autonomous systems, which relies on Machine Learning (ML) and AI applications when combined with fail-operational requirements renders the Verification and Validation (V&V) of these new systems a challenging endeavor. Prime examples are Advanced Driver-Assistance Systems (ADAS) that are prone to various safety/security vulnerabilities. The XANDAR project aims at developing a mature SW toolchain (from requirements analysis to the actual code integration on target including V&V) fulfilling the needs of industry for rapid prototyping of interoperable and autonomous ES. Starting from a model-based system architecture, XANDAR will leverage automatic model synthesis and software parallelization techniques to achieve specific non-functional requirements setting the foundation for a novel (real-time, safety-, and security)-by-Construction paradigm.

The goal of the SMART4ALL EU funded project is to build capacity amongst European stakeholders via the development of self-sustained, cross-border experiments that transfer knowledge and technology between academia and industry. It targets Customized Low Energy Computing (CLEC) in the Cyber-Physical (CPS) and the Internet of Things (IoT) domains. The vision of the project will be mainly realized through funded (via open calls) Pathfinder Application Experiments (PAEs) that will enable the transformation of academic knowledge into products.It is important to mention that SMART4ALL sets forward the concept of marketplace which is offered as a service (Marketplace-as-a-Servtce or MaaS) that acts as one-stopsmart-stop by offering tools, HPC services, and platforms to the PAE grantees. The purpose of this paper is to present the SMART4ALL High-Performance Computing (HPC) infrastructure and services realized according to the Hardware-as-a-Service paradigm. The SMART4A11 HPC infrastructure includes CPU, Memory, GPU, storage as well as FPGA resources connected with high-speed links.

In the context of this paper, a shape tracking application based on landmark alignment is transformed to support implementation in Field Programmable Gate Arrays (FPGAs). Towards this direction, several challenges are posed since a) computational intensive operations have to be replaced by faster ones, b) specific loops have to be modified (e.g., unrolled) to support the implementation of operations in parallel with different hardware resources, c) multiple pretrained models have to be compared in terms of speed and accuracy, d) partial loading of the pre-trained models has to be examined in order to fit their parameters in the Block Random Access Memories (BRAMs) of the FPGA for faster access, and e) alternative arithmetic representations have to be evaluated for higher speed and reduced resources.The C++ Deformable Shape Tracking (DEST) implementation of face alignment that is based on an Ensemble of Regression Trees is employed in our approach. The DEST application uses Eigen library routines to implement algebraic operations which are proved to be quite slow. The achievements of this paper, concern the replacement of appropriate Eigen calls in time critical paths with fast C code that can be directly used to synthesize reconfigurable hardware implementations. The elimination of the computational intensive Eigen calls has already improved the speed of the face alignment application by more than 240 times. In this paper we examine how the modified source code structure of the DEST application can be used to address the challenges described above.

This paper introduces a Quaternion-based rotational representation of low power, low resource, commercial-of-the-shelf (COTS) IMU sensors, offering high accuracy, reliability and real time performance. A critical aspect of this work is the distributed implementation of the proposed solution that facilitates its integration with IoT platforms utilizing the MQTT communication protocol while efficiently applying a modified Madgwick's filter implementation to extract the sensor's orientation and rotation. Based on the proposed solution, sensor orientation outperforms conventional implementations based on previously widely applied methods like Euler Angles and effectively tackles important shortcomings such as a sluggish response and issues like Gimbal Lock. Comprehensive, experimental evaluation reveals that the proposed solution yields state-of-the-art accuracy, while being deployed on a typical, low-cost COTS sensor while delay measurements indicate a highly reliable and time constrained performance adequate for a wide range of real life scenarios.

One of the biggest challenges in multicore platforms is shared cache management, especially for data-dominant applications. Two commonly used approaches for increasing shared cache utilization are cache partitioning and loop tiling. However, state-of-the-art compilers lack efficient cache partitioning and loop tiling methods for two reasons. First, cache partitioning and loop tiling are strongly coupled together, and thus addressing them separately is simply not effective. Second, cache partitioning and loop tiling must be tailored to the target shared cache architecture details and the memory characteristics of the corunning workloads. To the best of our knowledge, this is the first time that a methodology provides (1) a theoretical foundation in the above-mentioned cache management mechanisms and (2) a unified framework to orchestrate these two mechanisms in tandem (not separately). Our approach manages to lower the number of main memory accesses by an order of magnitude keeping at the same time the number of arithmetic/addressing instructions to a minimal level. We motivate this work by showcasing that cache partitioning, loop tiling, data array layouts, shared cache architecture details (i.e., cache size and associativity), and the memory reuse patterns of the executing tasks must be addressed together as one problem, when a (near)-optimal solution is requested. To this end, we present a search space exploration analysis where our proposal is able to offer a vast deduction in the required search space.

The proper mapping of an application on a multi-core platform and the scheduling of its tasks are key elements to achieve the maximum performance. In this article, a novel hybrid approach based on integrating the Logic-Based Benders Decomposition (LBBD) principle with a pure Integer Linear Programming (ILP) model is introduced for mapping applications described by Directed Acyclic Graphs (DAGs) on platforms consisting of heterogeneous cores. The LBBD approach combines two optimization techniques with complementary strengths, namely ILP and Constraint Programming (CP), and is employed as a cut generation scheme. The generated constraints are utilized by the ILP model to cut possible assignment combinations aiming at improving the solution or proving the optimality of the best-found one. The introduced approach was applied both on synthetic DAGs and on DAGs derived from real applications. Through the proposed approach, many problems were optimally solved that could not be solved by any of the above methods (ILP, LBBD) alone within a time limit of 2 hours, while the overall solution time was also significantly decreased. Specifically, the hybrid method exhibited speedups equal to 4.2× for the synthetic instances and 10× for the real-application DAGs over the LBBD approach and two orders of magnitude over the ILP model.

Parallel architectures are nowadays not only confined to the domain of high performance computing, they are also increasingly used in embedded time-critical systems. The ARGO H2020 project1provides a programming paradigm and associated tool flow to exploit the full potential of architectures in terms of development productivity, time-to-market, exploitation of the platform computing power and guaranteed real-time performance. In this paper we give an overview of the objectives of ARGO and explore the challenges introduced by our approach.

The development of efficient methods for mapping applications on heterogeneous multicore platforms is a key issue in the field of embedded systems. In this article, a novel approach based on the Logic-Based Benders decomposition principle is introduced for mapping complex applications on these platforms, aiming at optimizing their execution time. To provide optimal solutions for this problem in a short time, a new hybrid model that combines Integer Linear Programming (ILP) and Constraint Programming (CP) models is introduced. Also, to reduce the complexity of the model and its solution time, a set of novel techniques for generating additional constraints called Benders cuts is proposed. An extensive set of experiments has been performed in which synthetic applications described by Directed Acyclic Graphs (DAGs) were mapped to a number of heterogeneous multicore platforms. Moreover, experiments with DAGs that correspond to two real-life applications have also been performed. Based on the experimental results, it is proven that the proposed approach outperforms the pure ILP model in terms of the solution time and quality of the solution. Specifically, the proposed approach is able to find an optimal solution within a time limit of 2 hours in the vast majority of performed experiments, while the pure ILP model fails. Also, for the cases where both methods fail to find an optimal solution within the time limit, the solution of the proposed approach is systematically better than the solution of the ILP model.

Due to the demographic change in western society, new challenges regarding healthcare of the elderly population are at the verge of surfacing. Since young people are not capable of sustaining an adequate healthcare for elderly people, new healthcare fields have to be devised. Recent advances in information and communication technology enable the support of elderly people in their domestic environment. The EU project RADIO will design of an old age compliant smart home environment which specializes in fulfilling the needs of elderly people. This is partially achieved through a mobile robot platform which serves as an assistant to the respective elderly person. Apart from this, the robot also functions as a mobile sensor platform. Under this context, unobtrusiveness is of paramount importance since the robot should be a natural participant of patients' daily life. This paper discusses such a healthcare facility, analyses its requirements and poses the challenges towards this direction.

No abstract available.

As processors and systems-on-chip increasingly become multicore, parallel programming remains a difficult, time-consuming and complicated task. End users who are not parallel programming experts have a need to exploit such processors and architectures, using state of the art fourth generation of high programming languages, like Scilab or MATLAB. The ALMA toolset addresses this problem by receiving Scilab code as input and produces parallel code for embedded multiprocessor systems on chip, using platform quasi-agnostic optimisations. In this paper, coarse grain parallelism extraction and optimization issues as well as parallel code generation for the ALMA toolset are discussed.

Recently, system designers are facing the challenge of developing systems that have diverse features, are more complex and more powerful, with less power consumption and reduced time to market. These contradictory constraints have forced technology providers to pursue design solutions that will allow design teams to meet the above design targets. In that respect, this paper introduces an innovative technology platform, called MORPHEUS, which intents to provide complete design framework for dealing with the aforementioned challenges. MORPHEUS consists of a state of the art architecture that encompasses heterogeneous reconfigurable accelerators for implementing on the same hardware architecture applications with varying characteristics and a tool chain that, through a software oriented approach, eases the implementation of highly complex applications with heterogeneous characteristics. The proposed approach has been tested and evaluated through state of the art cases studies borrowed from complementary application domains.

The mapping process of high performance embedded applications to today's multiprocessor system on chip devices suffers from a complex tool chain and programming process. The problem here is the expression of parallelism with a pure imperative programming language which is commonly C. This traditional approach limits the mapping, partitioning and the generation of optimized parallel code, and consequently the achievable performance and power consumption of applications from different domains. The Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of a Scilab-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from high level of abstraction. This holistic solution of the toolchain allows the complexity of both the application and the architecture to be hidden, which leads to a better acceptance, reduced development cost, and shorter time-to-market. Driven by the technology restrictions in chip design, the end of exponential growth of clock speeds, and an unavoidable increasing request of computing performance, ALMA is a fundamental step forward in the necessary introduction of novel computing paradigms and methodologies.

Nowadays Wireless Sensor Networks are increasingly accepted as a reliable solution to highly demanding and critical application scenarios such as military and medical environments, where security support is an absolute prerequisite. However, supporting security implies the execution of cipher algorithms posing significant overheads on WSN nodes, which suffer from scarce resource availability. Moreover, the system wide overheads imposed by requirements related to network performance and behavior are not adequately addressed in current literature. In that direction, this paper intends to evaluate these effects for critical network parameters. The results presented are based on existing results reported in literature measurements concerning the performance overhead imposed by widely utilized encryption algorithms that have been developed for prominent WSN platforms. To evaluate the measurements, the execution performance of three popular cipher algorithms, has been integrated in Omnet++/MiXiM, a well known and widely utilized WSN network simulator. As part of this work, critical insights are provided concerning the system wide effect of deploying security algorithms which are not taken into account when focusing solely in the security algorithm measurements. Furthermore, important trade-offs are provided both qualitatively and quantitatively.

Low power techniques in a FPGA implementation of the hash functions called JH and Fugue are presented in this paper. The JH hash function is under consideration for adoption as standard. Pipeline technique (with some variants) and the use of embedded RAM blocks are the techniques in order to reduce the power consumption. Power consumption reduction between 6.3% and 33 % was achieved for JH function and similar a power reduction between 1.7% and 13.3 % was achieved for Fugue by means of the proposed techniques compared with the implementation without any low power issue.

During the last years, a new type of systems-on-chip called, reconfigurable systems-on-chip (RSoCs), has appeared. The design of such systems is a complex task and requires innovative methods to support the development process. In this paper, the authors present two alternative approaches for the efficient architecture exploration of RSoCs, based on SystemC language and on OCAPI-xl environment. The approaches introduced, allow early evaluation of alternative mappings of system's functionality onto different architectures. As a result, the time consuming iterations from lower design stages are eliminated and reduced design time is achieved. The paper proves the effectiveness of the proposed approaches through three different case studies, borrowed from complementary domains