We present a novel design methodology covering multiphysics simulation workflows for microring-based dense wavelength division multiplexing (DWDM) Silicon Photonics (SiPh) circuits used for high-performance computing systems and data centers. The main workflow is an electronics-photonics co-simulation comprising various optical devices from a SiPh process design kit (PDK), electronic circuits designed with a commercial CMOS foundry's PDK, and channel S-parameter models, such as interposers and packages, generated by using a full-wave electromagnetic (EM) solver. With the co-simulation, electrical and optical as well as electro-optical behaviors can be analyzed at the same time because best-in-class electronics and photonic integrated circuit simulators interact with each other. As a result, not only optical spectrum and eye diagrams but also electrical eye diagrams can be evaluated on the same simulation platform. In addition, the proposed methodology includes a statistical- and thermal-aware photonic circuit simulation workflow to evaluate process and temperature variations as well as estimate the required thermal tuning power as those non-idealities can lead to microring's resonance wavelengths shifting. For this, thermal simulation is conducted with a 3D EM model which is also used for such signal and power integrity analysis as a channel link simulation and IR drop. Also, photonic circuit simulations are performed where a design exploration and optimization of such microring's design parameters as Q-factor, and bias voltages are required to select the most promising designs, for example, to satisfy a specific bit-error rate. With the proposed design methodology having those multiphysics simulation workflows, DWDM SiPh can be fully optimized to have reliable system performance.

Photonic integrated circuits suffer from large process variations. Effective and accurate characterization of the variation patterns is a critical task for enabling the development of novel techniques to alleviate the variation challenges. In this study, we propose a hierarchical approach that effectively decomposes the spatial variations of silicon microring-based optical transceivers into wafer-level, intra-die, and inter-die components. We then demonstrate that the characterized variation models can be used to generate trustworthy synthetic data for architecture- and system-level solutions for variation alleviation. We further demonstrate the utility of our variation characterization method for accurate yield prediction based on partial measurement data.

High-speed optical interconnects are a promising solution for the rapidly increasing bandwidth density demands in data center and high-performance computing applications. This paper presents a transmitter that consists of a co-packaged optically injection-locked quantum-dot (QD) microring laser and a 28nm CMOS driver. Optical injection locking provides an effective solution to overcome the inherent low modulation bandwidth (≤ 5 GHz) of the QD microring laser. Further bandwidth extension is provided with the driver's asymmetric 2-tap feed-forward equalizer (FFE) that compensates the laser's non-linear optical dynamics. Combining these techniques allows for a record 22Gb/s operation of an O-band quantum-dot laser heterogeneously integrated in a silicon photonic platform.

Microring-based silicon photonic transceivers are promising to resolve the communication bottleneck of future high-performance computing systems. To rectify process variations in microring resonance wavelengths, thermal tuning is usually preferred over electrical tuning due to its preservation of extinction ratios and quality factors. However, the low energy efficiency of resistive thermal tuners results in nontrivial tuning cost and overall energy consumption of the transceiver. In this study, we propose a hybrid tuning strategy which involves both thermal and electrical tuning. Our strategy determines the tuning direction of each resonance wavelength with the goal of optimizing the transceiver energy efficiency without compromising signal integrity. Formulated as an integer programming problem and solved by a genetic algorithm, our tuning strategy yields 32%~53% savings of overall energy per bit for measured data of 5-channel transceivers at 5~10 Gb/s per channel, and up to 24% saving for synthetic data of 30-channel transceivers, generated based on the process variation models built upon measured data. We further investigated a polynomial-time approximation method which achieves over 100x speedup in tuning scheme computation, while still maintaining considerable energy-per-bit savings.

Skin-inspired electronics emerges as a new paradigm due to the increasing demands for conformable and high-quality skin-sensor-silicon (SSS) interfacing in wearable, electronic skin and health monitoring applications. Advances in ultra-thin, flexible, stretchable and conformable materials have made skin electronics feasible. In this paper, we prototyped an active electrode (with a thickness ≤ 2 um), which integrates the electrode with a thin-film transistor (TFT) based amplifier, to effectively suppress motion artifacts. The fabricated ultra-thin amplifier can achieve a gain of 32 dB at 20 kHz, demonstrating the feasibility of the proposed active electrode. Using atrial fibrillation (AF) detection for electrocardiogram (ECG) as an application driver, we further develop a simulation framework taking into account all elements including the skin, the sensor, the amplifier and the silicon chip. Systematic and quantitative simulation results indicate that the proposed active electrode can effectively improve the signal quality under motion noises (achieving ≥30 dB improvement in signal-to-noise ratio (SNR)), which boosts classification accuracy by more than 19% for AF detection.

High-performance low-cost flexible hybrid electronics (FHE) are desirable for internet of things (IoT). Carbon-nanotube (CNT) thin-film transistor (TFT) is a promising candidate for high-performance FHE because of its high carrier mobility (25cm2/V.s), superior mechanical flexibility/stretchability, and material compatibility with low-cost printing and solution processes. Flexible sensors and peripheral CNT-TFT circuits, such as decoders, drivers and sense amplifiers, can be printed and integrated with thinned (<;50μm) silicon chips on soft, thin, and flexible substrates for appealing product designs and form factors. Here we report: 1) process design kit (PDK) to enable FHE design automation, from device modeling to physical verification, and 2) open-source and solution-process proven intellectual property (IP) blocks, including Pseudo-CMOS [1] digital logic and analog amplifiers on flexible substrates, as shown in Figure 1. The proposed FHE-PDK and circuit design IP are fully compatible with silicon design EDA tools, and can be readily used for co-design with both CNT-TFT circuits and silicon chips.

Flexible Electronics (FE) is emerging for wearables and low-cost internet of things (IoT) nodes benefiting from its low-cost fabrication and mechanical flexibility. Combining FE with thinned silicon chips, known as flexible hybrid electronics (FHE), can take advantages of both low-cost printed electronics and high performance silicon chips. To design a FHE system, the process design kit (PDK) offering the capabilities for circuit design, simulation and verification for both FE and silicon chips is needed. The key elements of FHE-PDK include technology files for design rule checking (DRC), layout versus schematic (LVS) and layout parasitics extraction (LPE), as well as SPICE-compatible models for flexible thin-film transistors (TFTs) and passive elements. Wafer scale measurements are used to validate our SPICE models and design rules are derived accordingly to assure a satisfactory yield. With FHE-PDK, circuit and system designers can therefore focus on design innovations and can rely on design tools to produce manufacturable designs.

Nanophotonic interconnects have started replacing traditional electrical interconnects in data centers for rack-level communications and demonstrated great potential at board and chip levels. However, microring-based silicon photonic transceivers, an important element for nanophotonic interconnects, are very sensitive to fabrication process variations, and require power hungry wavelength tuning. In this paper, we apply efficient optimization algorithms to mix-and-match a pool of fabricated transceiver devices with the objective of minimizing the overall tuning power. This optimal pairing technique, applied during the production stage, reduce power consumption for wavelength tuning. For two sets of fabricated devices, the pairs of transceivers assigned by the optimal pairing technique reduce the tuning power by 6% to 60%. We further evaluate the method on synthetic data sets that are generated from a well-established process variation model. Our experimental results show that even greater power saving can be achieved when more fabricated devices are available for pairing and the runtime of the optimization algorithm is quite scalable.

Carbon nanotube thin film transistor (CNT-TFT) is a promising candidate for flexible electronics, because of its high carrier mobility and great mechanical flexibility. An accurate and trustworthy device model for CNT-TFTs, however, is still missing. In this paper, we present a SPICE-compatible compact model for CNT-TFT circuit simulation and validate the proposed model based on fabricated CNT-TFTs and Pseudo-CMOS circuits [1][2]. The proposed CNT-TFT model enables circuit designers to explore design space by adjusting device parameters, supply voltages and transistor sizes to optimize the noise margin (NM) and power-delay product (PDP), which are the key merits for larger scale CNT-TFT circuits. We further propose a design framework to effectively optimize the NM and PDP to facilitate greater automation of flexible circuit design based on CNT-TFTs.

The comb laser-driven microring-based dense wavelength division multiplexing silicon photonics is a promising candidate for next-generation optical interconnects. However, existing solutions for exploring the power-performance trade-off of such systems have been restricted to a limited design space, resulting from the unnecessary constraints of using an identical spacing for laser comb lines and microring channels, and of utilizing consecutive laser comb lines for data transmission. We propose an energy-efficient channel alignment scheme that aligns the microring channels to a subset of laser comb lines that are non-uniformly distributed in the free spectrum range of the microrings. Based on a well-established process variation model, our simulations show that the proposed scheme significantly reduces the microring tuning power in the presence of denser comb lines. The power saved from microring tuning can improve the overall system energy efficiency despite some power wasted in unused laser comb lines. We further conducted a case study for design space exploration using the proposed channel alignment scheme, seeking the most energy-efficient configuration in order to achieve a target aggregated data rate.

Flexible electronics is promising for a number of emerging applications such as foldable smartphone, wearables and internet of things (IoT) [1], [2], [3]. However, the key elements of flexible electronics, the thin-film transistors (TFT), often suffer from large process variations and inferior reliability. There is also a lack of trustworthy compact models for these devices. This paper gives an overview of design challenges for the flexible circuits, introduces a robust design style, Pseudo-CMOS, that has been widely used for digital TFT designs, and highlights the development of a flexible hybrid electronics process design kit (FHE-PDK) supporting design automation and verification of flexible hybrid electronics.

Flexible electronics is a promising technology for wearable applications. The flexible printed thin-film transistor (TFT) circuits, however, often suffer from large process variations and inferior long-term reliability. This paper describes recent progress on robust printed circuits, including a novel design style known as Pseudo-CMOS, which was invented [1] to tackle design challenges for flexible TFT circuits. With post-fabrication tuning capability, Pseudo-CMOS can survive large process variations which are inevitable for the low-cost printing process. Furthermore, degradation of circuit performance, either due to variations or aging, can be recovered by means of an external tuning circuit. The paper also illustrates some design examples of Pseudo-CMOS circuits for applications to energy [2], healthcare [3], biomedical [4], and near-field communication (NFC) tags [5], [6].

Printed electronics (PE) on flexible substrates is a promising technology for wearables and internet of things (IoT). To implement an integrated system on flexible substrates for applications ranging from medical imaging to disposable thermometers, robust design methodology based on unreliable printed components plays a critical role. This paper reviews robust design of printed circuits based on thin-film transistors (TFT). A novel design style known as Pseudo-CMOS [1], which can tackle several design challenges of TFT circuits, is also introduced. Design examples of Pseudo-CMOS circuits for applications in energy [2], healthcare [3], biomedical [4], and near-field communication (NFC) tags [5], [6] are discussed.

Short-reach nanophotonic interconnects are promising to solve the communication bottleneck in data centers and chip-level scenarios. However, the nanophotonic interconnects are sensitive to process and thermal variations, especially for the microring structures, resulting in significant variation of an optical link's bit error rate (BER). In this paper, we propose a power-efficient adaptive tuning approach for nanophotonic interconnects to address the variation issues. During the adaptive tuning process, each nanophotonic interconnect is adaptively allocated just enough power to meet the BER requirement. The proposed adaptive tuning approach could reduce the photonic receiver power by 8% - 34% than the worst-case based fixed design while achieving the same BER. Our evaluation results show that the adaptive tuning approach scales well with the process variation, the thermal variation and the number of communication nodes, and can accommodate different types of NoC architectures and lasers.

Moore's Law has set great expectations that the performance of information technology will improve exponentially until at least the end of this decade. Although the physics of silicon transistors alone might allow these expectations to be met, the physics of the long metal wires that cross and connect packages almost certainly will not. Global-level interconnects incorporating large-scale integrated photonics fabricated on the same platform as silicon microelectronics hold the promise of revolutionizing computing by enabling parallel many-core and network switch architectures that combine unprecedented performance and ease of use with affordable power consumption. Over the last decade, remarkable progress has been made in research on low-power silicon photonic devices for interconnect applications, and CMOS-compatible fabrication technologies promise a “Moore's Law for photonics” that could completely change the economics of integrated optics. In this survey, photonic technologies amenable to large-scale CMOS integration are reviewed from the perspective of high-performance interconnects operating over distance scales of 1mm to 100m. An overview of the requirements placed on integrated optical devices by a variety of modern computer applications leads to discussions of active and passive photonic components designed to generate, guide, filter, modulate, and detect light in the telecommunication bands. Critical challenges and prospects for large-scale integration are evaluated with an emphasis on silicon-on-insulator as a platform for photonics.

We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance, memory and inter-core bandwidths will also have to scale by orders of magnitude. Pin limitations, the energy cost of electrical signaling, and the non-scalability of chip-length global wires are significant bandwidth impediments. Recent developments in silicon nanophotonic technology have the potential to meet these off- and on-stack bandwidth requirements at acceptable power levels. Corona is a 3 D many-core architecture that uses nanophotonic communication for both inter-core communication and off-stack communication to memory or I/O devices. Its peak floating-point performance is 10 teraflops. Dense wavelength division multiplexed optically connected memory modules provide 10 terabyte per second memory bandwidth. A photonic crossbar fully interconnects its 256 low-power multithreaded cores at 20 terabyte per second bandwidth. We have simulated a 1024 thread Corona system running synthetic benchmarks and scaled versions of the SPLASH-2 benchmark suite. We believe that in comparison with an electrically-connected many-core alternative that uses the same on-stack interconnect power, Corona can provide 2 to 6 times more performance on many memory intensive workloads, while simultaneously reducing power.

A significant performance limitation in integrated circuits has become the metal interconnect, which is responsible for depressing the on-chip data bandwidth while consuming an increasing percentage of power. These problems will grow as wire diameters scale down and the resistance-capacitance product of the interconnect wires increases hyperbolically, which threatens to choke off the computational performance increases of chips that we have come to expect over time. We examine some of the quantitative implications of these trends by analyzing the International Technology Roadmap for Semiconductors. We compare the potential of replacing the global electronic interconnect of future chips with a photonic interconnect and see that there is in principle a four order of magnitude bandwidth-to-power ratio advantage for the latter. This indicates that it could be possible to dramatically improve chip performance without scaling transistors but rather utilize the capability of existing transistors much more efficiently. However, at this time it is not clear if these advantages can be realized. We discuss various issues related to the architecture and components necessary to implement on-chip photonic interconnect.