An approach to error-control coding is described for systems in which digit as well as symbol errors and erasures can occur, a symbol being a position-fixed group of digits. Codes that can deal with both types of errors and erasures simultaneously are constructed. A theoretical basis for determination of the error-control capacity of such codes is given.>

For a linear block code it is shown how the number of computations needed for the determination of an optimal encoder/decoder pair can be reduced by using the code's automorphism group. Furthermore, it is shown that the use of an unequal-error-protection-optical generator matrix and a minimum-weight coset leader decoder is suboptimal for a q-ary symmetry channel, but their determination needs less computational effort.>

In automated manufacturing the two-dimensional representation of product identification numbers by means of square dot codes offers a number of advantages over the use of bar codes. In this paper a method is described for the encoding of product identification numbers into square matrices of round dots on a contrasting background. It consists of an optimal source coding scheme for the encoding of identification numbers into channel message words, and a channel coding scheme offering error-detection and error-correction for random bit errors (dot corruptions). For the channel coding scheme, a special class of error-correcting codes is introduced, called {\em square-cyclic codes.} It is shown how to transform quasi-cyclic and (shortened) cyclic codes into square-cyclic codes.

The construction, properties, and decoding of four nonequivalent[4,2]codes over the alphabet{0,1}^{8}are described. These codes are able to correct the following error patterns:1)error patterns containing one nonzero byte,2)error patterns containing up to three nonzero bits, and3)error patterns containing one byte erasure and at most one nonzero bit. In addition, all error patterns containing one byte erasure and two nonzero bits can be detected. These codes can be used in the

A well-known technique for providing tolerance against single hardware component failures is triplication of the component, called triple modular redundancy (TMR). In this paper a component is taken to be a processor-memory configuration where the memory is organized in a bit-sliced way. If voting is performed bitwise in an orthodox TMR configuration consisting of three of these components, failure of a complete component or failure of bit-slices not on corresponding positions in the memories can be tolerated. We present a TMR technique, not using more redundancy than orthodox TMR, that can tolerate the failure of arbitrary bit-slices (including those on corresponding positions) up to a certain amount. Additionally it can tolerate the failure of arbitrary bit-slices up to a certain amount whenever one component is known to be malfunctioning or whenever one component is disabled. This generalized TMR technique is described for processor-memory configurations processing 4-, 8-, and 16-bit words, respectively.

The methods for combining codes, such as the direct sum, direct product, and|u|u + v|constructions, concatenation, etc., are extended to linear unequal error protection codes.

It is possible for a linear block code to provide more protection for selected positions in the input message words than is guaranteed by the minimum distance of the code. Linear codes having this property are called linear unequal error protection (LUEP) codes. Bounds on the length of a LUEP code that ensures a given unequal error protection are derived. A majority decoding method for certain classes of cyclic binary UEP codes is treated. A list of short (i.e., of length less than 16) binary LUEP codes of optimal (i.e., minimal) length and a list of all cyclic binary UEP codes of length less than 40 are included.