This paper presents the design and implementation of a pocket-sized electronic system for quantifying glucose levels in diabetic patients by measuring a byproduct of the chemical reaction of glucose oxidation, such as hydrogen peroxide. A novel Nano Wire sensor obtained the current versus the hydrogen peroxide (H2O2) concentration relationship. The system utilizes a modified amperometric electrochemical sensor circuit topology named "Strong Follower" (SF) to measure current signals from 1 μA to 11 μA accurately. The SF circuit includes active control loop feedback to maintain the output voltage in line with the input voltage, ensuring accurate and stable measurements. Simulation and experimental results demonstrate the effectiveness of the proposed system in quantifying H2O2 concentrations. Experimental tests were conducted using currents of 1, 5, 10, and 15 μA. Additionally, using general-purpose electronic components helps reduce the overall implementation cost, making it more accessible for diabetes healthcare applications.

A fully differential, power-efficient class AB Miller op-amp with accurate control of the output quiescent current is introduced. It can drive a wide range of resistive (200$\Omega$-1M$\Omega$) and capacitive loads (5pF-300pF). It has large dynamic and static current efficiencies of 8.6 and 7.9 and small-signal figures of merit higher than 7.4 for (1M $\Omega-200\Omega$) resistive load.

A new approach to design super class AB operational transconductance amplifiers (OTAs) with enhanced large-signal and small-signal performance is presented. It is based on employing two nested positive and negative feedback loops at the active load of an adaptively biased differential pair in weak inversion region. As a result, DC gain, gain-bandwidth product, settling time and noise are improved compared to conventional super class AB OTAs without extra circuit nodes or power consumption. Measurement results of a 180 nm CMOS test chip prototype show a current boosting factor higher than 5000 and a nearly ideal current efficiency. Due to the ultra-low quiescent currents and high driving capability, the circuit exhibits an excellent large-signal figure-of-merit (FOML) of 236 V-1. To illustrate the applicability of the proposed approach, a differential sample-and-hold (S/H) circuit was designed and fabricated on the same test chip. Measurement results of the S/H validate the advantages of the proposal.

This paper presents the experimental evaluation of a Differential Pair with Active Loads (DPAL), designed and fabricated with a 0.5 μm CMOS process, when operated at a bias current of 1 nA and a power supply of 1 V. The objective is to verify that this circuit can properly perform analog functions while dissipating 1 nW. Therefore, experimental measurements that demonstrate its functionality, power dissipation and leakage currents are presented; the results indicate that it is possible to implement extreme low power analog circuits with this process.

A micropower regulated cascode CMOS current mirror is presented, combining floating gate and quasi floating gate MOS transistors to achieve both wide swing and class AB operation, respectively. Measurement results for a 0.5 μm CMOS test chip prototype are included, showing that the current mirror can provide a THD at 100 kHz of -44 dB for a supply voltage of ±0.75 V and input current amplitudes 20 times larger than the bias current.

A super class AB recycling folded cascode amplifier in 130 nm CMOS is presented. It combines for the first time adaptive biasing of the differential input pair, nonlinear current mirrors with current starving and dynamic biasing of the cascode transistors in the output branch. Measurements using a ±0.5V supply show slew rate and gain bandwidth product improvement factors of 26 and 112 versus the conventional topology for the same bias currents, yielding the highest combined FoM to date.

A simple technique to greatly enhance the DC open-loop gain of a Miller op-amp is introduced here. It is based on the utilization of nested regulated cascode amplifiers. It uses conventional Miller compensation and does not increase the supply voltage. The proposed scheme has a DC open-loop gain Figure of Merit FoMAOLDC=24,614kV/V.pF.MHz/μWatt. It is especially appropriate for utilization in modern deep sub-micrometer CMOS technologies with low intrinsic gain.

A CMOS fully integrated all-pass filter with an extremely low pole frequency of 2 Hz is introduced in this paper. It has 0.08-dB passband ripple and 0.029-mm2Si area. It has 0.38-mW power consumption in strong inversion with ±0.6-V power supplies. In subthreshold, it has 0.64-μW quiescent power and operates with ±200-mV dc supplies. Miller multiplication is used to obtain a large equivalent capacitor without excessive Si area. By varying the gain of the Miller amplifier, the pole frequency can be varied from 2 to 48 Hz. Experimental and simulation results of a test chip prototype in 130-nm CMOS technology validate the proposed circuit.

A simple technique to implement highly power efficient class AB-AB Miller op-amps is presented in this paper. It uses a composite input stage with resistive local common mode feedback that provides class AB operation to the input stage and essentially enhances the op-amp's effective transconductance gain, the dc open-loop gain, the gain-bandwidth product, and slew rate with just moderate increase in power dissipation. The experimental results of op-amps in strong inversion and subthreshold fabricated in a 130-nm standard CMOS technology validate the proposed approach. The op-amp has 9 V·pF/μs·μW large-signal figure of merit (FOM) and 17 MHz · pF/μW small-signal FOM with 1.2-V supply voltage. In subthreshold, the op-amp has 10 V · pF/μs · μW large-signal FOM and 92 MHz · pF/μW small-signal FOM with 0.5-V supply voltage.

This paper describes a bandwidth (BW)- and slew rate (SR)-enhanced class AB voltage follower (VF). A thorough small signal analysis of the proposed and a state-of-the-art AB-enhanced VF is presented to compare their performance. The proposed circuit has 50-MHz BW, 19.5-V/ $\mu \text{s}$ SR, and a BW figure of merit of 41.6 (MHz $\times $ pF/ $\mu \text{W}$ ) for $C_{L} = 50$ pF. It provides 13 times higher current efficiency and 15 times higher BW than the conventional VF with equal 60- $\mu \text{W}$ static power dissipation. The experimental and simulation results of a fabricated test chip in the 130-nm CMOS technology validate the proposed circuit.

Reduction of minimum supply requirements is a crucial aspect to decrease the power consumption in VLSI systems. A high-performance capacitance multiplier able to operate with supplies as low as ±0.25 V is presented. It is based on adaptively biased class-AB current mirrors which provide high current efficiency. Measurement results of a factor 11 capacitance multiplier fabricated in 180-nm CMOS technology verify theoretical claims. Moreover, low-voltage precision rectifiers based on the same class-AB current mirrors are designed and fabricated in the same CMOS process. They generate output currents over 100 times larger than the quiescent current. Both proposed circuits have 300-nW static power dissipation when operating with ±0.25-V supplies.

A micropower single-stage folded cascode amplifier able to drive a wide range of capacitive loads is presented. It features class AB operation and includes power-efficient adaptive biasing techniques, which provide enhanced dynamic output current boosting and gain-bandwidth product (GBW). Phase lead compensation is used to improve phase margin and settling performance for low capacitive loads. Measurement results for a 0.5 μm CMOS process show a FoM of 5540 MHz pF/mA, the highest one reported to date for a folded cascode amplifier to the authors' knowledge.

The design of various current followers for the implementation of OTAs with high slew rate and current efficiency is addressed. Two basic current follower topologies are compared, and modifications of both followers to improve these parameters are presented. As an application example, an enhanced recycling folded cascode OTA is proposed. Measurement results of the OTA fabricated in a 0.5 μm CMOS process show a 260% and 180% improvement in SR and GBW, respectively, for the same power consumption.

Low voltage continuous and discrete time schemes for operation of analog circuits are presented. These are gate driven schemes based on floating batteries that extend the headroom of the differential input stage. This allows them to operate with down to 0.55 V total supply voltage and with transistors in strong/moderate inversion. A continuous-time amplifier and a switched capacitor circuit are shown as application examples of the proposed low voltage techniques.

An ultra low voltage low power AC coupled amplifier operating with supplies as low as ±0.18 V in 180 nm CMOS technology and a power dissipation of 0.15 μW is introduced. It has digitally programmable gain in the range from 1 to 15 and true constant bandwidth from 0.7 Hz to 2 kHz that is independent on gain. Experimental results from a test chip validate the proposed circuit. Additionally, simulations of the same PGA in 130 nm CMOS technology show that the proposed scheme operates with ±0.08 V supplies, total power dissipation of 0.07 μW and true constant bandwidth from 7.5 Hz to 8 kHz.

A novel technique for adaptive frequency compensation in negative feedback amplifiers is proposed. It is demonstrated that a simple reconnection of the compensation capacitor in a two-stage Miller op-amp leads to a pseudoconstant bandwidth for a moderate range of closed-loop gains, without requiring additional power dissipation or extra silicon area. Also, an improvement of power-supply rejection ratio is obtained. The presented technique has been applied to a non-inverting amplifier, which has been fabricated in a 0.18-μm CMOS process. Measurement results validating the proposed compensation scheme are provided.

This paper introduces a simple approach for the implementation of rail-to-rail operational amplifiers (OpAmps) with constant gmusing only one differential input pair. It is based on the utilization of switched voltage followers that introduce a DC level shift when the OpAmp's common mode input voltage is lower than the headroom of the input differential pair (DP). Additional circuitry is introduced in order to make the DP tail current insensitive to common mode input voltage variations. This improves CMRR and PSRR and reduces gmvariations. The additional circuitry increases power dissipation by less than 20%. Simulation results are presented that verify rail-to-rail operation with ±1.65 supply voltages in 0.5μm CMOS technology.

This paper presents a novel adaptive bias technique based on the use of squaring circuits. Here, the tail current of an operational amplifier (OpAmp) is controlled using an auxiliary circuit. By design, it generates a well-controlled tail current which - to a first order approximation - is independent of the OpAmp's common-mode input voltage. As a result, parameters like common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are enhanced. However, when a differential input signal is applied, it generates a tail current proportional to the square of the OpAmp's differential input voltage. In this way, the currents of the OpAmp's input pairs are boosted, thus improving slew rate. Experimental results in 0.5 μm CMOS technology verify current and slew rate enhancement factors between 10 and 15 with less than 20% static current increase.

A third-order Gm-C Chebyshev low-pass filter based on a novel gain-boosted tunable transconductor is presented. The transconductor employs local negative feedback for linearization controlling the drain voltage of the input transistors biased in the triode region. The gain boosted feedback amplifier is based on quasi-floating gate MOS transistors and its adjustable biasing current allows tuning the cutoff frequency of the filter. The filter is intended to be used in the baseband section of a zero-IF bluetooth low energy receiver and it has been fabricated in a standard 0.13-μm CMOS technology with a nominal cutoff frequency of 500 kHz. The power consumption of the overall filter is 450 μW with a supply voltage of 1.2 V. The measurement results show a third-order intermodulation distortion of -46.4 dB for two input tones located at the passband of the filter. The filter occupies a silicon area of 0.08 mm2.

A simple and power efficient scheme for input rail-to-rail Op-Amp operation with constant gmand CMRR over the common mode input range is introduced. The input stage uses complementary differential pairs but only one pair is active at a time. Three implementations of the scheme are discussed. They use very compact control circuitry to turn only one of the differential pairs at a time. Simulations and experimental verification of the proposed scheme are provided from a test chip prototype in 0.5μm CMOS technology.

A new family of two stage op-amps with broadband open loop response is introduced. These have a significant reduction of the DC open loop gain and maintain a high gain at frequencies as low as 1 Hz. This provides them with low DC offset. The proposed circuits are based on the Quasi-Floating Gate (QFG) technique, using a novel implementation for active loads that provides a very low effective resistance at DC and very-low frequencies without penalizing the high resistance at the pass band gain significantly. Moreover, a wide-band AC coupling structure also based on QFG transistors has been combined with the proposed technique, rejecting both the differential input DC voltage and the offset introduced by the circuit. These features make the proposed op-amps suitable for biological signal processing, where small amplitude signals are commonly affected by large DC offsets. Cadence simulation results employing a 0.5 micrometers technology are provided for validating the proposed circuits.

A very simple power supply rejection ratio (PSRR) enhancement technique is presented. It is suitable, among others, for low voltage power low power (LVLP) DC circuits such as biasing circuits. It is shown that a high insensitivity to AC noise in supply rails can be achieved with an almost zero contribution to the total internal noise. This is achieved at the expense of very small additional circuitry and no additional power dissipation or supply requirements. Simulation and experimental verification of these characteristics is provided.

Various class AB two-stage op-amps with high and approximately symmetrical slew rate and very simple architecture are introduced in this brief. A current replicating branch with scaled-down transistors in combination with adaptive loads is used to implement a push-pull output stage with maximum output current several times higher than the bias current. Postlayout simulation and measurement results are presented and verify a 400%-500% slew rate and 80%-100% GB enhancement with only 5% additional quiescent power dissipation and 20% silicon area increase.

A technique based on the use of Floating Gate MOS (FGMOS) transistors is proposed to improve the continuous tuning of CMOS transconductors. It can be applied to tuning circuits based on resistive current division, and allows significantly improving the linearity and input and output range the transconductor. Measurement results of a test chip prototype show an increase in IM3 of 13 dB for two input tones of 1Vpp, 950 kHz and 1050 kHz.

A simple improvement to Lazzaro's Winner Take All (WTA) circuit is introduced. It allows lowering the voltage supply requirements so that it can be functional in fine line CMOS technology. A low voltage Rank Order Filter is derived from the WTA using current starving techniques. Electrical measurements of a prototype in CMOS 0.5μm technology verify the operation of the WTA circuit with VDD = 1.5V. Simulations in PSpice show the functionality of a Rank Order Circuit using the same principle.

A compact analog multiplier/divider circuit operating in current-mode is presented featuring low supply voltage, low area requirements and wide dynamic range. It is suited to standard digital CMOS processes and can be successfully employed in a wide range of analog signal processing applications. Measurement results for a 0.5μm CMOS test chip prototype are presented. The circuit consumes 120μW using a single supply voltage of 1.5V and requires a silicon area of 150μm × 140μm.

A tunable CMOS transconductor is presented. Input rail-to-rail operation is achieved using floating-gate MOS (FGMOS) transistors. Tuning is also obtained using FGMOS transistors, which are biased in weak or moderate inversion to achieve precise output current scaling. A technique to set the proper transconductance value independently of process or temperature variations is also included. Measurement and simulation results using a 0.5um CMOS technology are presented to confirm all the circuits and strategies proposed.

Four novel compact differential pair (DP) topologies with enhanced transconductance gain are introduced: direct positive feedback DP, quasi floating gate DP, floating gate DP and tunable quasi floating gate DP. All of them use positive feedback to achieve gmenhancement and have the same supply requirements as the conventional differential pair. Results for 0.13 μm CMOS designs supplied at 1.0 V show that 5 to 10 gmenhancement factors are easily achieved with very small additional hardware and without increasing power dissipation.

A simple and power efficient approach for the implementation of continuous-time common mode feedback networks using a capacitive averaging network is introduced. It is shown that low voltage, continuous-time, fully differential rail to rail operation can be achieved using the proposed technique. This at the expense of very small additional hardware and no additional power dissipation One stage, two stage, telescopic and folded cascode op-amps are discussed as application examples.

Three novel CMOS capacitance scaling schemes, a comparison between them and some different classic schemes are presented. The novel topologies which use a modified second generation current conveyor, an improved current mirror and a current steering configuration of OTA provide higher values of Q and better frequency responses than the classical structures using basic current mirror schemes, as the simple current mirror and two different cascode current mirrors. Simulation results for the six different studied schemes are presented.

In this paper we discuss an efficient implementation of the Cherry-Hooper amplifier scheme based on a new OTA structure. This is used to design highly linear CMOS amplifiers with programmable and accurate gain and high bandwidth that remains approximately constant with gain adjustment. A fully differential VGA with 30 MHz approximate constant bandwidth and accurate digitally adjustable gain from 1 to 128 in 0.5 mum CMOS technology is discussed. Experimental verification of the proposed scheme is also provided.

This paper describes the application of the quasi-floating gate technique to overcome the common mode sensitivity of the degeneration MOS resistors, which results in a significant linearity improvement and an enhanced CMRR. The proposed approach requires minimal additional hardware, does not require increased supply voltages or additional quiescent power dissipation and preserves the possibility of tuning the MOS resistor value through small gate voltage variations. Results from two different linearized MOS source degeneration schemes implemented in a 0.5μm CMOS technology verify the feasibility of the presented solution

This paper presents the design and preliminary results of a full differential sample-and-hold circuit based on the “flipped voltage follower” (FVF) cell. The heart of this circuit is a fully differential low-voltage OTA based on FVF technique. The use of the FVF reduces the supply power requirements in the OTA. To overcome input sampling switches limitation imposed by the low supply voltage we make use of a low-voltage low stress and reliable clock signal doubler. It is evidenced how different versions of theses cells, coined as ”flipped voltage follower (FVF)” and voltage doubler have been used in the past for many applications Preliminary simulation results in a 0.18 μm digital CMOS process show that a resolution greater than 8 bits can be obtained with a 1.0 V supply voltage using a 1 MHz clock signal. Further investigations on the performance limit of the proposed method as well as reliability concerns will be performed on the experimental test chip.

Compact schemes to implement two highly linear four quadrant CMOS transconductance multipliers are presented in this work. They are based on floating gate transistors and/or source degeneration resistor which provide high linearity and wide input, output swing. Two cross connected differential pairs are used as current steering elements which provide continuous adjustable gain. Unlike the conventional multipliers the proposed techniques generate currents that have mostly linear terms and reduce cancellation of non-linear terms at the output. Hence they are very linear and non-vulnerable to practical problems like mismatch and finite output impedance. Simulation and Experimental results are provided which validate the proposed schemes.

A novel CMOS highly linear tunable pseudo-differential transconductor is presented. By using different linearization techniques, a new fully CMOS OTA has been designed that outperforms previous CMOS pseudo differential OTA implementations in terms of linearity. It has been designed in a 0.5 mum-CMOS technology with a single 3.3 V voltage supply. Experimental results show a IM3 of -72 dB for a 1 Vpp input signal at 2 MHz with a current consumption under 5 mA. A large tuning range is obtained with the IM3 always under -70 dB for the same input signal.

Class A/AB and class AB/AB two stage op-amps with very high and symmetrical slew rate are introduced. They use output dominant pole with phase lead compensation. Resistive local common mode feedback is used to achieve a class AB output stage. One of the architectures uses also a class AB pseudo-differential pair to achieve class AB operation in the input stage. Experimental results verify slew rate enhancement factors of 12 and 50 for the A/AB and AB/AB circuits respectively. This is achieved with same bandwidth and noise and very small additional quiescent power dissipation or hardware complexity.

A novel CMOS linear transconductor is presented. It is basically an improvement of the classical telescopic cascode OTA with source degeneration in which the resistor has been implemented using quasi-floating-gates transistors. It also allows compact implementation of common mode voltage control circuitry in order to save area and power consumption. This transconductor has been designed in a 0.5 μm CMOS technology and the results obtained show a THD of −61 dB at 10 Mhz for a 1 Vppoutput voltage. In order to show the feasibility for the implementation of tunable Gm-C filters using the proposed transconductor, a 1MHz tunable third order Chebyshev low-pass filter suitable for Bluetooth applications has been experimentally validated.

Programmable linear resistors are usually implemented using MOS transistors biased in the triode region. Recently a technique, based on quasi-floating-gate transistors, has been introduced to linearize the V-I characteristic of a MOS transistor operating in the ohmic region. In this paper an improved programmable linear resistor also based on quasi-floating gate techniques is presented, which provides a larger conductance than the conventional fixed gate-voltage implementation and features better performance in terms of linearity.

This paper proposes a novel very linear tunable transconductor based on local feedback loops. The linear V-I conversion is accomplished using MOS resistors based on quasi-floating gate transistors. The absence of current mirrors in the signal path provides low sensitivity to transistor mismatch and decrease of nonlinear distortion. The OTA was designed in a 0.5 μm CMOS technology with ±1.65-V supply voltage. Simulation results show a THD of -80 dB at 100 kHz with 1 Vpp input signal. Good linearity of the OTA over a large tuning range is obtained.

A highly linear voltage-to-current (V/I) converter is presented. A variant of the FVF denoted "flipped folded voltage follower" (FFVF) and a useful application in a voltage-to-current (V/I) converter are presented. A modification using floating gates to provide gain programmability is discussed. Simulation and experimental results of fabricated test chip show the high linearity of the scheme

A novel squarer circuit is proposed. The circuit operates in class AB yielding maximum output currents not limited by the quiescent currents. Class AB operation at the input stage is achieved using a compact pseudo-differential pair. Measurement results for a 0.5μm CMOS technology are included that demonstrate the approach followed.

Singled ended and fully differential low-voltage programmable gain amplifiers are presented. They have close to rail-to-rail input/output swing, and wide bandwidth. The operation is based on the technique of the floating voltage controlled voltage source in the feedback loop of an op-amp. Experimental results are shown that validate the proposed design in 0.5mum CMOS technology with a single supply VDD=1.5V and with NMOS and PMOS threshold voltages of 0.73V and 0.93V respectively.

This paper presents a new CMOS transconductor amplifier able to achieve 90dB of SFDR. It is based in the creation of low impedance nodes using local feedback to drive a degeneration resistor. Then, the current generated at the resistor is delivered directly to the output using source coupled pairs. The proposed transconductor does not rely on current mirrors or in cancellation of nonlinear terms, thus improving significantly the linearity and the robustness against mismatch. Simulation results are provided that show THD of 91 dB and an IM3 of 81 dB at 10MHz with 2Vpp differential input-output signal.

Class-AB circuits, which are able to deal with currents several orders of magnitude larger than their quiescent current, are good candidates for low-power analog design. This paper presents a new, simple, low-voltage class-AB unity-gain buffer, based on the flipped voltage follower cell. Simulation and experimental results are provided

A novel technique is proposed to achieve highly linear programmable voltage-to-current (V-I) converters over a rail-to-rail input range. It employs two passive resistors with one of their terminals tied to a very low impedance node to achieve an almost distortionless V-I conversion for rail-to-rail input signals. The resistor currents are conveyed to the output via programmable floating-gate MOS current mirrors that work in moderate inversion, thus achieving transconductance tuning in a wide range while preserving linearity in the rail-to-rail input range. Initial charge of the floating gates is removed during fabrication. An implementation fabricated in a 0.5-/spl mu/m CMOS technology using a dual supply of /spl plusmn/1.5 V achieves a THD of -60 dB over a wide transconductance tuning range with differential input swings equal to the total supply voltage. The area and power consumption are 0.1 mm/sup 2/ and 2.6 mW.

A new implementation of a resistorless and capacitorless scheme for continuous time highly linear weighted additions is presented. It is based on a circuit denoted "flipped folded voltage follower". Simulation and experimental results from a test chip prototype in 0.5mum technology validate the proposed circuit

A new family of high performance buffers is introduced. It is characterized by very low output impedance, wide signal range, wide bandwidth, and low power dissipation, no DC level shift between input and output terminals and class AB operation. The proposed circuits are validated with simulations in 0.5mum CMOS technology and with experimental results

A low voltage two stage operational amplifier with class AB output stage is presented, featuring simplicity and efficiency. It has a large effective output current boosting factor (~50) and close to a factor 2 bandwidth enhancement. This is achieved at the expense of minimum additional circuitry with no extra static power dissipation. Experimental verification of the characteristics of the proposed circuit is provided

A new dynamic biasing scheme for cascode transistors is introduced. It is applied to extend the input range of current mirrors and telescopic op-amps. The implementation of the proposed technique requires minimum additional circuitry and negligible power consumption and it does not increase the voltage requirements of the circuits. It is shown that besides extended signal range, improved gain accuracy is also achieved. Experimental results of a fabricated test chip in 0.5mum CMOS technology are presented that verify the proposed technique

Two versions of a compact and highly linear CMOS OTA, with two decades gain tuning range are presented. They use a fixed gain linear V-I conversion input stage and electronically programmable current mirrors working in triode mode. Programmability is achieved by tuning the drain-source voltage of the mirroring transistors. The OTA input range is independent of gain adjustment. Experimental results of a test chip in 0.5mum CMOS technology validate the OTA characteristics with distortion less than 0.5% over the entire tuning range

A new circuit for multiple-input voltage-mode min/max circuits that, unlike conventional implementations, do not have large voltage swings at any of the internal nodes, is discussed. This scheme is characterized by high-speed, high-precision and simple architecture. The proposed circuit exhibits linear complexity with the number of inputs. A test chip prototype with a three-input max circuit has been designed and built in a 0.8 /spl mu/m CMOS technology and experimental results are shown that verify the proposed approach.

A fully integrated CMOS implementation of a continuous-time analog median filter is presented. The array median filter uses two compact analog circuits as building blocks to implement the variable delay and median detection. Median detectors are based on transconductance comparators to speed their time response, while the time delay is implemented using all-pass filters. Both circuits allow modular expansion for the implementation of large sized median filter array processors. In addition, a fast novel technique for parallel image processing is presented. It is shown that an image of 91/spl times/81 pixels is processed in less than 30 /spl mu/S using an array of high-speed analog processors. Experimental results of a test chip prototype in 2 /spl mu/m CMOS technology MOSIS process are presented.

Two new CMOS low-voltage linear transconductors for High Frequency (HF) applications are presented. They use tunable floating voltage sources between the input and the transistor gates of each inverter that forms the transconductor proposed by Nauta (1992). Two implementations of the floating batteries are presented. The proposed transconductors operate under constant low voltage supply as low as 1.2 V and transconductance and output resistance are independently tunable. It is suitable to be used in HF continuous time filters with programmable center frequency and quality factor. To this end, simulation results of a 10.7 MHz band-pass g/sub m/-C filter operating at a voltage supply of 1.5 V and large input swing are presented.

This paper presents a new CMOS low-voltage linear transconductor for Very High Frequency (VHF). It uses multiple-input floating-gate transistors (MIFGTs) in each inverter that forms the differential transconductor presented by Nauta (1992). The proposed transconductor operates under constant low-voltage supply as low as 1.2 V and its transconductance and output resistance are independently tunable. It is suitable for use in HF continuous time filters with programmable center frequency and quality factor. To this end, simulation results of a 10.7 MHz and Q=40 g/sub m/-C filter operating with a voltage supply of 1.4 V and with rail-to-rail input swing are presented.

Simple class-AB CMOS voltage and current precision rectifier circuits that operate from a single supply close to a transistor's threshold voltage are introduced. The current rectifier has output voltage swings comparable to the supply voltage and the voltage rectifier has wide input and output swings. Simulations of both rectifiers operating at 20 MHz are shown. Experimental results of a test chip are presented that verify the proposed circuits. A full wave precision rectifier based on the proposed rectifier cells is discussed.

A linear voltage-to-current converter that operates with a single supply voltage close to a transistor's threshold voltage and that has almost rail-rail input and output swings is introduced. The circuit is conceived as an input interface for current-mode signal processing systems. It also has applications for the implementation of other very low-voltage circuits like instrumentation amplifiers and common mode feedback control circuits. Simulations and experimental results of a test chip prototype in 1.2 /spl mu/m CMOS technology are presented that verify the functionality of the proposed circuit and its broadband characteristics.

An implementation of a low-voltage analog defuzzifier module is introduced. It employs low distortion, very compact analog multipliers with multiple-input floating gate transistors. Experimental and simulation results from a test chip verify the proposed scheme. The total harmonic distortion of the multiplier is less than 0.1% and its silicon area is only 180/spl times/150 /spl mu/m/sup 2/ in 2 /spl mu/m CMOS technology. Orbit 2 um low-noise N-well MOSIS fabrication technology has been used for the fabrication of test chip prototypes. A new scheme for the modular expansion of analog defuzzifiers with arbitrary number of rules and outputs variables is presented.

A four quadrant analogue multiplier that operates with a 1.4 V single supply and 0.6 V peak-peak input signals on both inputs is presented. It is based on a new low-voltage class AB differential amplifier with quiescent current control. Current efficiency and random distortion are introduced as quality factors to evaluate the performance of the analog multiplier. The multiplier presented here is characterized by a high current efficiency (50%), high bandwidth (40 MHz) and a high linearity (<1% distortion). Experimental results of a test chip are shown that verify low-voltage, low distortion and wide swing operation. Post layout simulations are presented that verify its wide bandwidth characteristics.

Adaptive filters have been traditionally developed in a digital environment which involves a large number of computations to derive the coefficients of the desired approximation. Most of the time, these calculations required a machine of great capacity and that is not practical for some applications like channel equalization in cellular systems. This paper proposes a continuous-time adaptive filter which is based on representing the impulse response of an adaptive filter as a linear combination of a set of orthogonal exponentials. An important practical advantage is that if a satisfactory representation can be obtained by exponentials simple filter structures can be synthesized. An analog adaptive filter structure that improve the time convergence of conventional realizations using a continuos time LMS algorithm to reduce the error between the reference system and the adaptive filter is shown.

A novel BiCMOS membership function circuit is presented. It implements trapezoidal/triangle functions with all parameters (slope, position, width, height and amplitude) independently and continuously adjustable. Computer simulations are shown that verify the characteristics of the circuit.

Architectures of VLSI fuzzy processors based on voltage-mode and novel current-mode defuzzification schemes are discussed. The processors use fully programmable circuits building blocks. The proposed schemes allow modular expansion of the fuzzy processor. SPICE simulations are shown that verify the processors.

A simple CMOS current-mode filter is presented. Its basic building block is a transconductor. It is comprised of a MOS transistor driver operating in the triode region cascoded with a MOS transistor current source at the output. This circuit can be employed in high-frequency continuous-time current-mode filters using a /spl plusmn/1 V power supply while dissipating less than 1 mW of power. To illustrate the methodology a second-order fully-differential bandpass filter with programmable f/sub 0/ and Q tuning is demonstrated. This filter dissipates less than 0.5 mW/pole with a /spl plusmn/1 V power supply and occupies an area of 0.6 mm/sup 2/ using a MOSIS Orbit 2 /spl mu/m CMOS technology.>

An efficient membership function circuit for the analog VLSI implementation of fuzzy controllers and for piecewise linear approximation is discussed. It is an analog BiCMOS circuit that approximates a triangular function with programmable height, slope and horizontal position. The circuit is very compact and operates on /spl plusmn/1.65 V supplies. Experimental results of a test chip are presented.>

A current mirror with low input voltage requirements is presented. Its application to implement high performance current sensors for IDDQ testing is discussed. Experimental results show that the circuit can operate with an input voltage of 0.2 V. Simulations show feasibility of the circuit to operate as a high speed built-in current sensor with minimum disturbance on the circuit under test.>

Class AB wide range programmable linear current mirrors in bipolar and CMOS technology are presented. Bipolar mirrors can operate with /spl plusmn/0.75 V supplies, CMOS mirrors with /spl plusmn/1.5 V supplies. They are characterized by an approximately constant bandwidth that is independent of the gain adjustment. Experimental and simulation results are shown to verify the proposed structures.>

Class AB differential amplifiers using composite BiCMOS and bipolar transistors are introduced. Their utilization for the implementation of low voltage (+-1.65 V) operational amplifiers with high slew rate and rail to rail common mode input voltage range is discussed.>

Two approaches for current-mode filters derived from canonical control structures are discussed. One of the approaches uses only lossy integrators. Both use transconductance multipliers to implement programmable transfer function coefficients. Experimental results are presented that verify the biquadratic structures.>

A chip to solve Laplace equation in real time using analog VLSI circuits is described. It uses MOS transistors in ohmic mode to simulate a two dimensional array of resistive cells that can be configured as a programmable resistor, as an open (empty) cell or as a voltage source (boundary) cell. The cell and the overall system architecture are discussed.>

This paper presents a new method for detecting defect and fabrication variations in both digital and analog CMOS circuits by simultaneously pulsing the power supply rails and analyzing the temporal and/or the spectral characteristics of the resulting transient rail currents. The method presented has a distinct advantage over other forms of i/sub DD/ testing because it requires a single test vector to excite and expose the presence of a defect or irregular fabrication process condition. This paper presents data from simulations and defective IC's supporting this technique.>

An area optimized computer-aided cascade switched-capacitor (SC) filter design program called AROMA is presented. The program contains several user-selectable filter approximation techniques. AROMA permits the user to make tradeoffs between several design parameters such as passive sensitivity, op-amp output voltage swings, clock frequency, and the total capacitance of the filter. The program has default values of the tradeoffs, however, each block in the cascade filter can be modified by the user to meet specific requirements. AROMA incorporates recent results of practical interest to the SC filter designer. The flexible structure of the program allows for easy addition of new results, i.e., refined efficient building blocks, additional filter approximations, etc. It can be used by the novice as well as by experienced designers. Furthermore, the program is user-oriented. It can start, in its simplest mode, with a set of frequency specifications. The output gives a circuit description file that can be layed out by an analog circuit layout generator program. Examples illustrating the practicalness of AROMA are given.