Demo Data from EDBT 2026 / reviewers in the wild / expert
Atreyi Chakraverti
dblp:42/2637
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1988
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 91% Integrated circuit design · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design › routing › VLSI routing
gate array routing |
0.0 | 1 | 1988 | Routing Algorithm for Gate Array Macro Cells · DAC 1988 |
Electronic design automation
physical design |
0.0 | 1 | 1988 | Routing Algorithm for Gate Array Macro Cells · DAC 1988 |
Electronic design automation › physical design
routing |
0.0 | 1 | 1988 | Routing Algorithm for Gate Array Macro Cells · DAC 1988 |
Integrated circuit design › ASIC design
gate array |
0.0 | 1 | 1988 | Routing Algorithm for Gate Array Macro Cells · DAC 1988 |
Methods — techniques the papers use, named apart from their topics
routing algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1988 | Routing Algorithm for Gate Array Macro Cells
Atreyi Chakraverti, Moon-Jung Chung |
DAC | 1 |