We present a configurable implementation of a convolution processing unit suitable for computing mixed-precision quantized neural networks. The design is implemented as a hardware generator written in Chisel, which is a software framework for writing hardware circuit generators. Our generator is designed to use minimal hardware resources and is very flexible in regards to various aspects of the convolution operation, including: image size, kernel size, image bitwidth, kernel bitwidth, activation function, and more. The processing unit is configurable only at generation time, thus we don’t pay the price of using more general hardware, instead we can tailor it to the problem at hand.

We present chisel4ml, a Chisel-based tool that generates hardware for highly quantized neural networks described in QKeras. Such networks typically use parameters with bitwidths less than 8 bits and may have pruned connections. Chisel4ml can generate the highly quantized neural network as a single combinational circuit with pipeline registers in between the different layers. It supports heterogeneous quantization where each layer can have a different precision. The full parallelization enables very low-latency and high throughput inference, that are required for certain tasks. We illustrate this on the triggering system for the CERN Large Hadron Collider, which filters out events of interest and sends them on for further processing. We compare our tool against hls4ml, a high-level synthesis based approach for deploying similar neural networks. Chisel4ml is still under development. However, it already achieves comparable results to hls4ml for some neural network architectures. Chisel4ml is available on https://github.com/cs-jsi/chisel4ml.

Setting up a reliable electric propulsion system in the automotive domain calls for a smart condition monitoring device that is able to reliably assess the state and the health of the electric motor. To allow massive integration of such monitoring devices, it is required of them to be low-cost and miniature. Those requirements pose limitations on their accuracy, however, we show in this paper that those limitations can be significantly reduced by suitably processing the sensor data. We used machine learning models (random forest and XGBoost) to transform very noisy measurements of motor winding insulation resistance measured by a low-cost device to the much more reliable value with which we are able to compete with measurements made by the state-of-the-art high-priced measuring system. The proposed methodology represents a crucial building block in future smart condition monitoring system and enables low-cost and accurate assessment of electric motor health connected to the state of its winding insulation.

Despite many decades of research on high-performance Deep Neural Network (DNN) accelerators, their massive computational demand still requires resource-efficient, optimized and parallel architecture for computational acceleration. Contemporary hardware implementations of DNNs face the burden of excess area requirement due to resource-intensive elements such as multipliers and non-linear Activation Functions (AFs). This paper proposes DNN with reused hardware-costly AF by multiplexing data using shift-register. The on-chip quantized log2 based memory addressing with an optimized technique is used to access input features, weights, and biases. This way the external memory bandwidth requirement is reduced and dynamically adjusted for DNNs. Further, high-throughput and resource-efficient memory elements for sigmoid activation function are extracted using the Taylor series and its order expansion have been tuned for better test accuracy. The performance is validated and compared with previous works for the MNIST dataset. Besides, the digital design of AF is synthesized at 45 nm technology node and physical parameters are compared with previous works. The proposed hardware reused architecture is verified for neural network 16:16:10:4 using 8-bit dynamic fixed-point arithmetic and implemented on Xilinx Zynq xc7z010clg400 SoC using 100 MHz clock. The implemented architecture uses 25% less hardware resources and consumes 12% less power without performance loss, compared to other state-of-the-art implementations, as lower hardware resources and power consumption are especially important for increasingly important edge computing solutions.

SRAM-based FPGA devices are becoming a suitable platform for implementing modern Systems On Programmable Chip (SOPC) due to their high reconfigurability, low cost and availability. The high performance SOPCs are often powered by multiple embedded microprocessors. FPGA devices are susceptible to radiation which causes soft-errors in their configuration memory. This paper proposes a soft error recovery technique for FPGA SOPC with multiple processors. The recovery algorithm runs on one of the embedded microprocessors at a time. The algorithm checks the configuration memory of the FPGA through the internal configuration access port and repairs a faulty configuration bit through partial reconfiguration. The technique also includes an extended recovery procedure where, upon the failure of the processor that runs the recovery algorithm, the error is recovered by another working processor. The proposed error recovery technique was verified by a case study and a fault emulation experiment.

We propose a low hardware overhead mechanism for internal FPGA configuration check and repair. The approach is effective against soft errors in the configuration memory (i.e., the errors caused by high energy radiation also known as Single Event Upsets). The proposed recovery mechanism occupies less hardware resources and has the shortest fault recovery time than the solutions reported so far.

FPGAs are subjected to SEU faults. Fault emulation methods are used to verify the behavior of the system in the presence of fault. In this paper an automated fault emulation approach is presented. An original, fully automated extraction of SEU fault sources is introduced and the injection procedure for various types of faults in FPGA configuration and user memory is explained. Faults are injected during run-time using an embedded microprocessor. Only the resources affected by the faults are reconfigured. A prototype fault injection tool was developed and the approach is demonstrated on two different FPGA applications, micro processor BIST, and AES BIST.

Oscillation-based test (OBT) is one of the approaches for measuring static ADC parameters such as differential nonlinearity (DNL) and integral nonlinearity (INL) that can be implemented in a built-in self-test arrangement. As demonstrated in the paper, due to the arbitrary input signal phase shift and non-coherent input signal two oscillation periods are possible. This in turn manifests itself as a measurement uncertainty that should be considered in practice.

In this paper we present the generalization of the test sequencing problem, originally defined for symmetrical tests, that also covers asymmetrical tests. We prove that the same heuristics that has been employed in the traditional solution of the problem (e.g., the AO* algorithm with heuristics based on Huffman's coding) can be employed also for the generalized case. Examples are given to illustrate the approach.

A new approach for analog circuit simulation and troubleshooting, based on the fuzzy logic paradigm, is presented in this paper. This approach allows to deal with soft faults, single or multiple ones, and with both impreciseness and uncertainty of information. It has been implemented in a system named FLAMES (Fuzzy Logic ATMS and Model-based Expert System), of which details are provided, together with different experimental results, for both simulation and troubleshooting processes.