For the past 25 years, the EDA industry has played a major role in the growth of the semiconductor industry, providing tools and services that have helped companies develop electronics products that permeate and improve every aspect of our daily lives.As the semiconductor industry moves into the nanometer era, they face many key questions when envisioning a new product. When do they want the product to reach the market? How will that product be differentiated? Where do they develop and manufacture that product?Less than a decade ago, these questions would have been answered completely independent of whatever EDA vendor a semiconductor company selected. However, in the nanometer era, the answers to these questions can be significantly influenced not only by EDA companies but also by the IP and pure-play foundries that make up the infrastructure of the semiconductor industry. In order to compete in a global marketplace, these companies must align their individual core competencies with those of the semiconductor industry to help IC companies create products with the optimal combination of performance, price, and time-to-market.In this panel, the CEOs of the three major EDA vendors, along with peers from the IP and manufacturing areas discuss these fundamental changes to the semiconductor industry, and the challenges of working together to help customers successfully bring new products to market.Jay Vleeschhouwer, a senior analyst for Merrill Lynch, will moderate a series of questions for the panelists from the customer's point of view that address how EDA, IP and pure-play foundries can impact the competitiveness of semiconductor companies and the products they develop.

Over the last 20 years, electronic design has grown to annual revenues of $3B per year and dominates the Technical and Systems Sector of the Software Industry. Cadence and Synopsys are among the top 20 independent software vendors when ranked by market capitalization. In short, the EDA industry has come of age, but the future of the industry is far from certain.

No abstract available.

Summary form only given. The amount of electrical engineering knowledge required in semiconductor design is decreasing and the process is now mimicking software design. Design re-use is moving upstream with sophisticated subsystems and flexible, technology-independent building blocks becoming available from ASIC vendors and other sources. The time spent debugging the applications software is vastly exceeding the development time invested in the hardware. Driven by the opportunity of million-plus gates ASICs on the one hand, sophisticated synthesis and simulation tools on the other, the design paradigm for most designers is shifting from the gate level to the functional level. With this shift comes the move to hardware description languages, increased design re-use, and active trade-off between software and hardware implementations. The author highlights the status and progress of this evolution and discusses its impact on semiconductor and system design in the coming years.>

This paper presents ESPRIT, an automatic test pattern generation (ATPG) system for testing single stuck-at faults in combinational logic. ESPRIT generates test patterns by performing fault simulation on random patterns derived from nonuniformly distributed input signal probabilities. The system computes input signal probabilities that minimize a testability cost function. Using ESPRIT, we have observed orders-of-magnitude reduction in the number of random trials required to obtain a given fault coverage.

In order to compare logic synthesis and optimization systems, a set of benchmarks has been submitted to a number of authors. The results obtained are reported in the present proceedings. This short paper introduces the benchmarks as well as a set of criteria to measure the quality of logic synthesis systems.

Article Free Access Share on SOCRATES: a system for automatically synthesizing and optimizing combinational logic Authors: David Gregory GE Calma Company Research Triangle Park, North Carolina GE Calma Company Research Triangle Park, North CarolinaView Profile , Karen Bartlett Department of Electrical Engineering University of Colorado at Boulder Department of Electrical Engineering University of Colorado at BoulderView Profile , Aart de Geus GE Calma Company Research Triangle Park, North Carolina GE Calma Company Research Triangle Park, North CarolinaView Profile , Gary Hachtel Department of Electrical Engineering University of Colorado at Boulder Department of Electrical Engineering University of Colorado at BoulderView Profile Authors Info & Claims DAC '86: Proceedings of the 23rd ACM/IEEE Design Automation ConferenceJuly 1986 Pages 79–85Online:02 July 1986Publication History 32citation279DownloadsMetricsTotal Citations32Total Downloads279Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

The automation of the synthesis and optimization of combinational logic can result in savings in design time, significant improvements of the circuitry, and guarantee functional correctness. Synthesis quality is often measured in terms of the area of the circuit on the chip, which fails to take into account the timing constraints that might be imposed on the logic. This paper describes SOCRATES, a synthesis system capable of generating combinational logic in a given technology under user-defined timing constraints. We believe this system is the first to perform optimized, delay-constrained, multilevel synthesis into standard cell libraries. Applied to a large number of examples, the system has successfully traded off area versus delay and performs optimized, delay-constrained, multilevel synthesis into standard cell libraries.