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Fumiya Tada

dblp:42/3209 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 92% Integrated circuit design · 8%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › high-level synthesis › register-transfer level synthesis
control logic synthesis		 0.011997
Design and Synthesis of Array Structured Telecommunication Processing Applications · DAC 1997
Electronic design automation
high-level synthesis		 0.011997
Design and Synthesis of Array Structured Telecommunication Processing Applications · DAC 1997
Electronic design automation
logic synthesis		 0.011997
Design and Synthesis of Array Structured Telecommunication Processing Applications · DAC 1997
Electronic design automation › physical design › routing › wire routing
maze routing		 0.011980
A fast maze router with iterative use of variable search space restriction · DAC 1980
Electronic design automation
physical design		 0.011980
A fast maze router with iterative use of variable search space restriction · DAC 1980
Electronic design automation › physical design
routing		 0.011980
A fast maze router with iterative use of variable search space restriction · DAC 1980
Electronic design automation
search-space pruning		 0.011980
A fast maze router with iterative use of variable search space restriction · DAC 1980

Methods — techniques the papers use, named apart from their topics

structured control logic design · 0.0array frames · 0.0
YearPublicationVenuePosition
1997 Design and Synthesis of Array Structured Telecommunication Processing Applications
abstract
This paper describes an automated design andsynthesis methodology for telecommunications ASIC's.Array frames, an array structured visualization of theprocessing problem, are used in the specification anddebugging of the design. This allows design much closer to thespecification level. The array frame concept is integratedinto the Dali structured control logic design environment. AnSDH (Synchronous Digital Hierarchy) style exampledemon-strates the use of array frames. The array frame approachwas successfully applied in industrial applications.
Wolfgang Meyer 0002, Andrew Seawright, Fumiya Tada
 DAC3
1980 A fast maze router with iterative use of variable search space restriction
abstract
This paper describes a new method of restricting search space for maze routing, to achieve a higher routing completion ratio and shorter machine time. The router is applied iteratively, expanding the width of L-shaped search space restriction from narrow one to wider ones successively. Using this method, machine time was reduced to one-fourth and the routing completion ratio was more than 10% higher in experimental comparison with singly restricted routers of no iteration. This paper also discusses an analysis to help to decide the iteration number and L-shaped path width.
Fumiya Tada, Kiyoshi Yoshimura, Takashi Kagata, Takeyoshi Shirakawa
 DAC1