EDBT 2026 Demo / reviewers in the wild / expert

Christian Rabedaoro

dblp:42/330 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 70% Reconfigurable computing and FPGAs · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › floorplanning
FPGA floorplanning		 0.011997
Synthesis and Floorplanning for Large Hierarchical FPGAs · FPGA 1997
Reconfigurable computing and FPGAs › FPGA architecture
hierarchical FPGA		 0.011997
Synthesis and Floorplanning for Large Hierarchical FPGAs · FPGA 1997
Electronic design automation
physical design		 0.011997
Synthesis and Floorplanning for Large Hierarchical FPGAs · FPGA 1997
Electronic design automation
logic synthesis		 0.011997
Synthesis and Floorplanning for Large Hierarchical FPGAs · FPGA 1997

Methods — techniques the papers use, named apart from their topics

hierarchical partitioning · 0.0divide-and-conquer · 0.0
YearPublicationVenuePosition
1997 Synthesis and Floorplanning for Large Hierarchical FPGAs
abstract
Because the VLSI circuits complexity growth, the trend in design is towards divide-and-conquer schemes, in which circuits are composed of blocks, standard macros or custom macros. From the other side, to allow an implementation of large digital circuits, increased capacity target FPGAs are organized hierarchically. In this paper, we present a hierarchical FPGA floorplanning method which takes into account both the hierarchy of the design and the hierarchy of the target. The method aims at minimization the timing and balancing cost of the floorplan and is based on automatic detection of macro blocks and assigning them to the target FPGA hierarchical zones.
Helena Krupnova, Christian Rabedaoro, Gabriele Saucier
 FPGA2