Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Michael Vinov

dblp:42/3422 · DBLP profile ↗
← Back
6ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Artificial intelligence and machine learning · 2Databases, data management, data science and information retrieval · 1Graphics, computer vision, multimedia, augmented reality and games · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Electronic design automation · 90% Processor architecture and microarchitecture · 10%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
hardware verification
0.122007
Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation · DAC 2007
Constraint-Based Random Stimuli Generation for Hardware Verification · AAAI 2006
Electronic design automation
hardware verification and test
0.122005
VLIW: a case study of parallelism verification · DAC 2005
Industrial experience with test generation languages for processor verification · DAC 2004
Electronic design automation › hardware verification and test
processor verification
0.122005
VLIW: a case study of parallelism verification · DAC 2005
Industrial experience with test generation languages for processor verification · DAC 2004
Electronic design automation › hardware verification and test › test generation › high-level test generation
system-level test generation
0.112007
Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation · DAC 2007
Electronic design automation › hardware verification and test
test generation
0.112007
Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation · DAC 2007
Processor architecture and microarchitecture › instruction-level parallelism › VLIW
VLIW processor
0.112005
VLIW: a case study of parallelism verification · DAC 2005

Methods — techniques the papers use, named apart from their topics

dynamic scenario interleaving · 0.1constraint solving · 0.1test program generator · 0.1parallel generation technique · 0.1
YearPublicationVenuePosition
2019 The SERUMS tool-chain: Ensuring Security and Privacy of Medical Data in Smart Patient-Centric Healthcare Systems
abstract
Future-generation healthcare systems will be highly distributed, combining centralised hospital systems with decentralised home-, work-and environment-based monitoring and diagnostics systems. These will reduce costs and injury-related risks whilst both improving quality of service, and reducing the response time for diagnostics and treatments made available to patients. To make this vision possible, medical data must be accessed and shared over a variety of mediums including untrusted networks. In this paper, we present the design and initial implementation of the SERUMS tool-chain for accessing, storing, communicating and analysing highly confidential medical data in a safe, secure and privacy-preserving way. In addition, we describe a data fabrication framework for generating large volumes of synthetic but realistic data, that is used in the design and evaluation of the tool-chain. We demonstrate the present version of our technique on a use case derived from the Edinburgh Cancer Centre, NHS Lothian, where information about the effects of chemotherapy treatments on cancer patients is collected from different distributed databases, analysed and adapted to improve ongoing treatments.
Vladimir Janjic, Michael Vinov, Thomas Given-Wilson, Axel Legay, Euan Blackledge, R. Arredouani, George Stylianou, Wanting Huang, Juliana Küster Filipe Bowles, Andreas Francois Vermeulen, Agastya Silvina, Marios Belk, Christos Fidas, Andreas Pitsillides, Michael Rossbory
IEEE BigData2
2019 Towards Specification of a Software Architecture for Cross-Sectoral Big Data Applications
abstract
The proliferation of Big Data applications puts pressure on improving and optimizing the handling of diverse datasets across different domains. Among several challenges, major difficulties arise in data-sensitive domains like banking, telecommunications, etc., where strict regulations make very difficult to upload and experiment with real data on external cloud resources. In addition, most Big Data research and development efforts aim to address the needs of IT experts, while Big Data analytics tools remain unavailable to non-expert users to a large extent. In this paper, we report on the work-in-progress carried out in the context of the H2020 project I-BiDaaS (Industrial-Driven Big Data as a Self-service Solution) which aims to address the above challenges. The project will design and develop a novel architecture stack that can be easily configured and adjusted to address cross-sectoral needs, helping to resolve data privacy barriers in sensitive domains, and at the same time being usable by non-experts. This paper discusses and motivates the need for Big Data as a self-service, reviews the relevant literature, and identifies gaps with respect to the challenges described above. We then present the I-BiDaaS paradigm for Big Data as a self-service, position it in the context of existing references, and report on initial work towards the conceptual specification of the I-BiDaaS software architecture.
Ioannis Arapakis, Yolanda Becerra 0001, Omer Boehm, George Bravos, Vasilis Chatzigiannakis, Cesare Cugnasco, Giorgos Demetriou, Iliada Eleftheriou, Julien-Etienne Mascolo, Lidija Fodor, Sotiris Ioannidis, Dusan Jakovetic, Leonidas Kallipolitis, Evangelia Kavakli, Despina Kopanaki, Nicolas Kourtellis, Mario Maawad Marcos, Ramon Martín de Pozuelo, Nemanja Milosevic, Giuditta Morandi, Enric Pages, Gerald H. Ristow, Rizos Sakellariou, Raül Sirvent, Srdjan Skrbic, Ilias Spais, Giorgos Vasiliadis, Michael Vinov
SERVICES28
2007 Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation
abstract
Parallelism in system architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. We report on a method for system-level test case generation. This method relies on dynamic interleaving of scenarios from the core level or sub-system level. We discuss the relevance of this method for the system level. We also describe a tool that implements this method and show how it was used in IBM for system verification of the Xbox 360 chip and power management in the cell processor, as well as verification of the pSeries eServers. We claim that this method shortened the system level verification cycle and allowed reuse in and across projects, which led to exposure of system-level bugs in a relatively short time.
Shady Copty, Itai Jaeger, Yoav Katz, Michael Vinov
DAC4
2006 Constraint-Based Random Stimuli Generation for Hardware Verification
Yehuda Naveh, Michal Rimon, Itai Jaeger, Yoav Katz, Michael Vinov, Eitan Marcus, Gil Shurek
AAAI5
2005 VLIW: a case study of parallelism verification
abstract
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper we report on the verification of a Very Large Instruction Word processor. The verification team used a sophisticated test program generator that modeled the parallel aspects as sequential constraints, and augmented the tool with manually written test templates. The system created large numbers of legal stimuli, however the quality of the tests was proved insufficient by several post silicon bugs. We analyze this experience and suggest an alternative, parallel generation technique. We show through experiments the feasibility of the new technique and its superior quality along several dimensions. We claim that the results apply to other parallel architectures and verification environments.
Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Lichtenstein, Michal Rimon, Michael Vinov, Massimo A. Calligaro, Andrew Cofler, Gabriel Duffy
DAC6
2004 Industrial experience with test generation languages for processor verification
abstract
We report on our experience with a new test generation language for processor verification. The verification of two superscalar multiprocessors is described and we show the ease of expressing complex verification tasks. The cost and benefit are demonstrated: training takes up to six months; the simulation time required for a desired level of coverage has decreased by a factor of twenty; the number of escape bugs has been reduced.
Michael L. Behm, John M. Ludden, Yossi Lichtenstein, Michal Rimon, Michael Vinov
DAC5