Owing to charger noise, inaccurate touch points and fake touch points may happen so that a device has a wrong behavior. The intensity of charger noise could be much larger than that of original touch signals. Besides, the frequency of charger noise varies for each different charger. Therefore, industry identifies charger noise as the most difficult problem in capacitive touch applications. The solution to the problem has become a key in the mobile market. In this paper, we prove that the combination of frequency hopping and repeated integration is an effective method to handle the problem. In addition, we propose an efficient discrete Fourier transform (DFT)-based algorithm to select a good sampling frequency. Moreover, we show an efficient hardware-software co-design adopting our method in Touch IC. Experimental results show that our method can increase SNR by 37 dB and find a good sampling frequency fast and dynamically.

Modern circuit placement, especially analog placement, often needs to consider various constraints, such as symmetry, proximity, preplaced, variant, fixed-boundary, minimum separation, boundary, and fixed-outline constraints, for better electrical effects and higher performance. To handle these diverse constraints, topological floorplan representations are pervasively used because of their higher flexibility and smaller solution space. Due to their intrinsic limitation in deriving module adjacency information directly from the representations themselves, however, they might incur difficulties in handling related constraints. In this paper, we work on B*-trees, which have been shown to be most effective and efficient for floor-plan/placement problems, and present a corner stitching compliant B*-tree (CB-tree, for short) to remedy the significant deficiency in its module adjacency handling. A CB-tree is a B*-tree integrated with modified corner stitching to offer much higher flexibility/efficiency, especially for adjacent module identification/packing. Compared with the previous works, CB-trees can achieve the lowest time complexity for module packing with the aforementioned constraints. Experimental results show that the CB-trees achieve the best solution quality and consume the least running time for industrial designs with various constraints. In particular, our work provides key insights into the handling of comprehensive placement constraints with a topological representation.

Optical Proximity Correction (OPC) is the most popular technique to handle design shape distortions arising from subwavelength lithography. Existing OPC models are typically very computationally expensive and thus not efficient to be incorporated for layout optimization. In this paper, we present an efficient, yet sufficiently accurate OPC cost model which can predict the optimal location of a wire segment for OPC optimization and give an upper bound of the interference amount, guaranteeing that the interference amount is never underestimated. Based on this cost model, we propose an OPC-aware wire perturbation algorithm for post-layout interconnect optimization. We show that the effects of wire perturbation have the concavity or monotonicity property which can dramatically reduce the search space for finding the optimal location of each wire for OPC optimization. Further, we can incrementally update the OPC cost of a wire by recomputing only the affected wires because of the property of superposition of our model. Experimental results show that our algorithm can efficiently obtain much better OPC results than a state-of-the-art OPC-friendly router, based on a leading commercial OPC tool.

Given a set of pins and a set of obstacles on routing layers, a multilayer obstacle-avoiding rectilinear Steiner minimal tree (ML-OARSMT) connects these pins by rectilinear edges within layers and vias between layers and avoids running through any obstacle to construct a Steiner tree with a minimal total cost. The ML-OARSMT problem is very important for many very large scale integration designs with pins being located in multiple routing layers that contain numerous routing obstacles incurred from IP blocks, power networks, prerouted nets, etc. As a fundamental problem with extensive practical applications to routing and wirelength/congestion/timing estimations in early design stages, it is desired to develop an effective algorithm for the ML-OARSMT problem to facilitate the design flow. However, there is no existing work on this ML-OARSMT problem. In this paper, we first formulate the ML-OARSMT problem with rectangular obstacles and then identify key different properties of this problem from its single-layer counterpart. Based on the multilayer obstacle-avoiding spanning graph, we present the first algorithm to solve the ML-OARSMT problem. Our algorithm can guarantee an optimal solution for any two-pin net and many multiple-pin nets. Experiments show that our algorithm results in 33% smaller total costs on average than a construction-by-correction heuristic which is widely used for Steiner-tree construction in the recent literature.

Given a set of pins and a set of obstacles on routing layers, a multi-layer obstacle-avoiding rectilinear Steiner minimal tree (ML-OARSMT) connects these pins by rectilinear edges within layers and vias between layers, and avoids running through any obstacle to construct a Steiner tree with a minimal total cost. The ML-OARSMT problem is very important for many VLSI designs with pins being located in multiple routing layers that contain numerous routing obstacles incurred from IP blocks, power networks, prerouted nets, etc. Therefore, it is desired to develop an effective algorithm for the ML-OARSMT problem. However, there is no existing work on this ML-OARSMT problem. In this paper, we first formulate the ML-OARSMT problem and identify key different properties of the problem from its single-layer counterpart. Based on the multilayer obstacle-avoiding spanning graph (ML-OASG), we present the first algorithm to solve the ML-OARSMT problem. Our algorithm can guarantee an optimal solution for any 2-pin net and many higher-pin nets. Experiments show that our algorithm results in 33% smaller total costs on average than a construction-by-correction heuristic which is widely used for Steiner-tree construction in the recent literature.