A built-in self-test (BIST) approach for functionality measurements, including noise figure (NF), linearity and frequency response of analog circuitry in mixed-signal systems, is presented. The BIST circuitry consists of a direct digital synthesizer (DDS) based test pattern generator (TPG) and a multiplier/accumulator based output response analyzer (ORA). The BIST approach has been implemented in hardware and used for actual NF measurements for comparison with measurements from external test equipment.

Most adaptive computing systems use reconfigurable hardware in the form of field programmable gate arrays (FPGAs). For these systems to be fielded in harsh environments where high reliability and availability are a must, the applications running on the FPGAs must tolerate hardware faults that may occur during the lifetime of the system. In this paper, we present new fault-tolerant techniques for FPGA logic blocks, developed as part of the roving self-test areas (STARs) approach to online testing, diagnosis, and reconfiguration . Our techniques can handle large numbers of faults (we show tolerance of over 100 logic faults via actual implementation on an FPGA consisting of a 20 times 20 array of logic blocks). A key novel feature is the reuse of defective logic blocks to increase the number of effective spares and extend the mission life. To increase fault tolerance, we not only use nonfaulty parts of defective or partially faulty logic blocks, but we also use faulty parts of defective logic blocks in nonfaulty modes. By using and reusing faulty resources, our multilevel approach extends the number of tolerable faults beyond the number of currently available spare logic resources. Unlike many column, row, or tile-based methods, our multilevel approach can tolerate not only faults that are evenly distributed over the logic area, but also clusters of faults in the same local area. Furthermore, system operation is not interrupted for fault diagnosis or for computing fault-bypassing configurations. Our fault tolerance techniques have been implemented using ORCA 2C series FPGAs which feature incremental dynamic runtime reconfiguration

We present an efficient approach for on-chip frequency response measurement, including phase and gain, of analog circuitry in mixed-signal systems. The approach uses direct digital synthesizer (DDS) to supply test sine waves with different frequencies and phases. The output response is analyzed using a multiplier and accumulator. The resultant phase delay measurement is used to correct other measurements such as gain and linearity for more accurate testing and characterization of the analog circuit under test. The approach was implemented in Verilog, synthesized in a field programmable gate array (FPGA), and used for frequency response measurements of an actual device under test.

We present a built-in self-test (BIST) approach based on a direct digital synthesizer (DDS) for functionality testing of analog circuitry in mixed-signal systems. A main contribution of this paper is the BIST-based hardware implementation and measurement of amplifier linearity (IP3) and frequency response, including both phase and gain. The approach has been implemented in Verilog and synthesized into a field-programmable gate array (FPGA), where it was used for functional testing of an actual device under test (DUT) and compared to simulation results.

We present a built-in self-test (BIST) approach based on direct digital synthesizer (DDS) for functionality testing of analog circuitry in mixed-signal systems. Of particular interest, and a main contribution of This work, is the BIST-based hardware implementation and measurement of amplifier linearity (IP3) test using DDS. The approach described in This work has been implemented in Verilog and synthesized into FPGAs where it was used for functional testing and compared to simulation results.

We describe the development of built-in self-test (BIST) for a generic SoC consisting of a field programmable gate array (FPGA) core for application specific logic along with a processor and several memory cores. Our target device was the Atmel AT94K series system-on-chip (SoC), also known as a field programmable system level integrated circuit (FPSLIC). The original goal for this project was to develop BIST configurations to completely test the programmable logic and routing resources of the FPGA core and then to use the FPGA core to test the other cores. We found that the FPGA can provide only limited testing of the some memory cores and even less testing of the processor. The processor, on the other hand, provides more effective testing of some memory cores than the FPGA core. In addition, the ability of the processor to write the FPGA configuration memory provides an improved and more efficient method of testing the FPGA core. As a result, the processor core was the primary testing resource instead of the FPGA.

We present the first online built-in self-test (BIST) and BIST-based diagnosis of programmable logic resources in field-programmable gate arrays (FPGAs). These techniques were implemented and used in a roving self-testing areas (STARs) approach to testing and reconfiguration of FPGAs for fault-tolerant applications. The BIST approach provides complete testing of the programmable logic blocks (PLBs) in the FPGA during normal system operation. The BIST-based diagnosis can identify any group of faulty PLBs, then applies additional diagnostic configurations to identify the faulty look-up table or flip-flop within a faulty PLB. The ability to locate defective modules inside a PLB enables a new form of fault-tolerance that reuses partially defective PLBs in their fault-free modes of operation.

We discuss the development of Built-In SelfTest (BIST) configurations that test all of the programmable logic and interconnect resources in the core of Xilinx 4000E, 4000XL/XLA and Spartan series Field Programmable Gate Arrays (FPGAs). While there has been prior work in BIST for these FPGAs, the fast-carry logic has not been addressed and only a small portion of the total interconnect resources has been targeted. The programmable logic is completely tested in two test sessions of 12 BIST configurations each, but the programmable interconnect resources requires as many as 206 BIST configurations. Therefore, we also discuss architectural features that affect the testability of the FPGA and, in turn, the number of BIST configurations needed by comparing the BIST configurations developed for these Xilinx FPGAs with those previously developed for other FPGAs.1

In this paper we show that an embedded FPGA core is an ideal host to implement infrastructure IP for yield improvement in a bus-based SoC. We present methods for testing, diagnosing, and repairing embedded FPGAs, for which complete testability is achieved without any area overhead or performance degradation. We show how an FPGA core can provide embedded testers for other cores in the SoC, so that cores designed to be tested with external vectors can be tested with BIST, and the entire SoC can be tested with a low-cost tester.

We present a Built-In Self-Test (BIST)-based diagnostic approach for the programmable interconnect resources in Field Programmable Gate Arrays (FPGAs) that can be used for either on-line or off-line testing. The technique was originally intended for on-line diagnosis of faulty interconnect to support fault-tolerant applications. However, the technique has been proven to be an excellent approach for off-line testing and diagnosis as well, providing high-resolution diagnostics with the ability to identify the faulty wire segment or programmable switch. We have implemented this BIST-based diagnostic approach on the ORCA series FPGA and present the results of testing and diagnosing known defective FPGAs.

We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable.

In this paper we present an on-line, multi-level fault tolerant (FT) technique for system functions and applications mapped to partially and dynamically reconfigurable FPGAs. Our method is based on the roving self testing areas (STARs) fault detection/location strategy presented in Abramovici et al. (1999). In STARs, the area under test uses partial reconfiguration properties to modify the configuration of the area under test without affecting the configuration of the system function and dynamic reconfiguration properties to allow uninterrupted execution of the system function while reconfiguration takes place. In this paper we take this one step further. Once a fault (or multiple faults) is detected we dynamically reconfigure the working area application around the fault with no additional system function interruption (other than the interruption when a STAR moves to a new location). We also apply the concept of partially usable blocks to increase fault tolerance. Our method has been successfully implemented and demonstrated on the ORCA 2CA series FPGAs from Lucent Technologies.

We present a BIST-based approach able to detect and accurately diagnose any single and most multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs). For any faulty PLB, we also identify its internal faulty modules or modes of operation. This accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs.

In this paper we explore the process of extracting potential bridging fault sites from the physical design database for VLSI devices by using standard extraction tools for fringe and overlap capacitance. We then use the extracted capacitance to create a list of potential bridging fault sites ordered to reflect the relative probability of a bridging fault occurring at each site. As a result, potential bridging fault sites can be rank-ordered for manufacturing test development such that the most likely site can be targeted first. In this way we improve the overall efficiency and effectiveness of the test development process. We have implemented this technique for the Delta 39K/sup TM/ series of complex programmable logic devices by Cypress Semiconductor and describe the results obtained.

In this paper we present a novel integrated approach to on-line FPGA testing, diagnosis, and fault-tolerance, to be used in high-reliability and high-availability hardware. The test process takes place in self-testing areas (STARs) of the FPGA, without disturbing the normal system operation. The entire chip is eventually tested by having (STARs) gradually rove across the FPGA. Our approach guarantees complete testing of programmable logic blocks and interconnect, and provides maximum diagnostic resolution. A new fault-tolerant (FT) technique allows using partially defective FPGA resources for normal operation, providing longer mission life-span in the presence of faults. We also introduce the basic concepts of a new dynamic FT method, spare resources needed to bypass a fault are always in the neighborhood of the located fault, thus simplifying fault-bypassing.

Four methods for accessing BIST for FPGAs via the IEEE 1149.1 standard boundary scan interface are presented and discussed in terms of advantages/disadvantages including their impact on test time and diagnostic resolution. These methods can be used in a variety of FPGA architectures for system level testing and diagnosis.

We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults affecting the programmable switches that configure the FPGA interconnect. As a result, the BIST technique provides complete testing of interconnect faults.

Testing requirements for the application of built-in self-test to fault tolerant circuits include: (1) detection of all single and multiple faults and (2) verification of correct circuit operation in the presence of faults. Modifications to built-in logic block observer (BILBO) and circular BIST are proposed which make these techniques satisfy both testing requirements. Evaluation of the two modified BIST approaches via single and multiple stuck-at fault simulation in conjunction with a random fault injection procedure indicate that the modified BILBO approach provides better testing results.

We describe a library of parameterized VHDL models for various concurrent fault detection circuits and maintenance functions developed for simulation and synthesis of ASICs which support on-line testing and diagnostics in systems designed for high reliability and availability. Issues associated with the selection and modeling of the various online testing functions are also discussed.

Accurate diagnosis is an essential requirement in many testing environments, since it is the basis for any repair or replacement strategy used for chip or system fault-tolerance. In this paper we present the first approach able to diagnose faulty programmable logic blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximal diagnostic resolution. Our approach is based on a new Built-In Self-Test (BIST) architecture for FPGAs and can accurately locate any single and most multiple faulty PLBs. An adaptive diagnostic strategy provides identification of faulty PLBs with a 7% increase in testing time over the complete detection test, and can also be used for manufacturing yield enhancement. We present results showing identification of faulty PLBs in defective ORCA chips.

We present a new approach for FPGA testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without area or performance penalties to the system function implemented by the FPGA, since the FPGA is reconfigured for normal system operation. An analysis of Look-Up Table (LUT) based FGPA architectures yields a general expression for the number of test sessions and establishes the bounds on FPGA logic resources required to minimize the number of BIST configurations required to completely test all of the programmable logic blocks of an FPGA.

We present an improved Built-In Self-Test (BIST) approach for the programmable logic blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures the FPGA as a group of C-testable iterative logic arrays. The new architecture is easily scalable with increasing size of FPGAs and ensures routability of the various configurations required to completely test the FPGA in three test sessions. In addition, the BIST approach addresses RAM mode testing as well as testing the adder/subtractor modes in FPGAs.

We present a new approach for Field Programmable Gate Array (FPGA) testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without any area overhead or performance penalties to the system function implemented by the FPGA. Our approach is applicable to all levels of testing, achieves maximal fault coverage, and all tests are applied at-speed. We describe the BIST architecture used to test all the programmable logic blocks in an FPGA and the configurations required to implement our approach using a commercial FPGA. We also discuss implementation problems caused by CAD tool limitations and limited architectural resources, and we describe techniques which overcome these limitations.

We present a novel approach for built-in self test (BIST) for VLSI. Many conventional BIST schemes use signatures generated by a linear feedback shift register (LFSR) or a multiple input signature register (MISR) for determining whether the device under test is faulty or fault free. In the approach presented, fault detection is made based on the number of different states the LFSR visits. This number is called the cycle length. It is also shown that such an approach results in the probability of aliasing of 2/sup -(2m-1+m/), where m denotes the number of registers in the LFSR, compared to 2/sup -m/ achieved by conventional signature analyzers. We also present the complexity of the additional hardware required to implement the scheme.

Efficient identification of all single bit errors in the input polynomial to signature analysis registers is achieved by using characteristic polynomial f(x)=f/sub a/(x)f/sub b/(x) where f/sub a/(x) and f/sub b/(x) have different degrees and are of the form f/sub n/(x)=x/sup n/+x/sup n-1/+1. The input polynomial must be of degree

The effect of compensating module faults on the reliability of majority voting based VLSI fault-tolerant circuits is investigated using a fault injection simulation method. This simulation method facilitates consideration of multiple faults in the replicated circuit modules as well as the majority voting circuits to account for the fact that, in VLSI implementations, the majority voting circuits are constructed from components of the same reliability as those used to construct the circuit modules. From the fault injection simulation, a survivability distribution is obtained which, when combined with an area overhead expression, leads to a more accurate reliability model for majority voting based VLSI fault-tolerant circuits. The new model is extended to facilitate the calculation of reliability of fault-tolerant circuits which have sustained faults but continue to operate properly. Analysis of the reliability model indicates that, for some circuits, the reliability obtained with majority voting techniques is significantly greater than predicted by any previous model.>

A practical application and case s,tudy of a Built-In Self-Test (BIST) technique for high-speed data-path circuitry is described. The approach has been implemented in six VLSI devices developed for broadband packet switching applications. The technique provides high fault coverage (> 90%) with low area overhead penalty (< 4%) and no impact to performance. The BIST approach is used for all levels of testing and, at the system level, performs full circuit board BIST with diagnostic resolution to the faulty component or interconnect.

The necessary conditions for designing testable static redundancy system-level fault-tolerant circuits are derived. In addition, algorithms are proposed for the efficient generation of test patterns for fault-tolerant circuits designed to satisfy these testability conditions. The test generation algorithm has been incorporated with an algorithm for the construction of majority voting devices and automated to produce a software package that generates testable fault-tolerant circuits along with test patterns to test the resultant circuit completely. As input, the algorithm requires a testable original circuit, along with an associated set of test patterns and the desired design parameters E, R, and K.>