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Kaushik Datta

dblp:42/3544 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
High-performance computing · 70% Parallel and multicore computing · 23% Processor architecture and microarchitecture · 7%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing › performance optimization
auto-tuning
0.112008
Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures · SC 2008
Parallel and multicore computing › parallel architecture
multicore optimization
0.112008
Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures · SC 2008
High-performance computing › performance engineering
performance portability
0.112008
Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures · SC 2008
High-performance computing
stencil computation
0.112008
Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures · SC 2008
Processor architecture and microarchitecture
chip multiprocessor
0.012008
Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures · SC 2008

Methods — techniques the papers use, named apart from their topics

optimization strategies · 0.1auto-tuning · 0.1
YearPublicationVenuePosition
2008 Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures
abstract
Understanding the most efficient design and utilization of emerging multicore systems is one of the most challenging questions faced by the mainstream and scientific computing industries in several decades. Our work explores multicore stencil (nearest-neighbor) computations - a class of algorithms at the heart of many structured grid codes, including PDE solvers. We develop a number of effective optimization strategies, and build an auto-tuning environment that searches over our optimizations and their parameters to minimize runtime, while maximizing performance portability. To evaluate the effectiveness of these strategies we explore the broadest set of multicore architectures in the current HPC literature, including the Intel Clovertown, AMD Barcelona, Sun Victoria Falls, IBM QS22 PowerXCell 8i, and NVIDIA GTX280. Overall, our auto-tuning optimization methodology results in the fastest multicore stencil performance to date. Finally, we present several key insights into the architectural tradeoffs of emerging multicore designs and their implications on scientific algorithm development.
Kaushik Datta, Mark Murphy, Vasily Volkov, Samuel Williams 0001, Jonathan Carter 0002, Leonid Oliker, David A. Patterson 0001, John Shalf, Katherine A. Yelick
SC1