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Young-June Park

dblp:42/3561 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 60% Integrated circuit design · 40%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › technology computer-aided design
device simulation
0.021994
A time dependent hydrodynamic device simulator SNU-2D with new discretization scheme and algorithm · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Mixed particle Monte Carlo method for deep submicron semiconductor device simulator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Integrated circuit design
analog and mixed-signal circuits
0.011994
A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation
design optimization
0.011994
A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Integrated circuit design › analog and mixed-signal circuits
device modeling
0.011994
A time dependent hydrodynamic device simulator SNU-2D with new discretization scheme and algorithm · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation › technology computer-aided design
hydrodynamic simulation
0.011994
A time dependent hydrodynamic device simulator SNU-2D with new discretization scheme and algorithm · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Integrated circuit design › digital circuit design › CMOS circuit design
digital CMOS circuits
0.011994
A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation › physical design › timing optimization
propagation delay optimization
0.011994
A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Integrated circuit design › semiconductor device modeling
drift-diffusion model
0.011991
Mixed particle Monte Carlo method for deep submicron semiconductor device simulator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Integrated circuit design
semiconductor device modeling
0.011991
Mixed particle Monte Carlo method for deep submicron semiconductor device simulator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991

Methods — techniques the papers use, named apart from their topics

transient simulation · 0.0hydrodynamic model · 0.0discretization scheme · 0.0base doping profile optimization · 0.0monte carlo · 0.0langevin equation · 0.0
YearPublicationVenuePosition
1994 A time dependent hydrodynamic device simulator SNU-2D with new discretization scheme and algorithm
abstract
A two-dimensional device simulator SNU-2D based on the hydrodynamic model is developed for the simulation and analysis of submicron devices. The simulator has the capacity for both self-consistent steady-state and transient-state simulation. To obtain better convergence and numerical stability, we adopt an improved discretization scheme for the carrier energy flux equation and a new strategy for the transient simulation. In steady-state simulation the new discretization scheme shows a considerable improvement in convergence rate and numerical accuracy compared with the existing schemes. A transient simulation study is carried out on a deep submicron n-MOSFET used in the sense amplifier of SRAM cells to investigate the gate-switching characteristic. It is found that the behavior of carrier temperature is quasi-static during the switching time even for very fast switching speed, while the behavior of impact ionization under transient mode deviates from that under dc mode as the switching speed increases.>
Woo-Sung Choi 0002, Jae-Gyung Ahn, Young-June Park, Hong-Shick Min, Chang-Gyu Hwang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
1994 A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays
abstract
Proposes an optimization procedure for the bipolar base doping profile for a high-speed BiCMOS circuit. This procedure aims to achieve the minimum propagation delay time, taking the power supply, the load capacitance, and the bipolar device layout into consideration. For a small load capacitance, the peak base doping concentration and the base width should be as small as possible. However, for a high load capacitance, the optimized base doping profile can vary under the emitter area constraint. Utilizing this optimization procedure, it will be shown that the propagation delay time can be reduced by more than 30% at the same MOS current (I/sub MOS/=1 mA) through the coordinated reduction of both the vertical doping profile and the horizontal dimensions of the bipolar transistor, with the power supply voltage scaled from 5 to 3.3 V.>
Ahmed S. Desouki, Young-June Park, Hong-Shick Min
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1991 Mixed particle Monte Carlo method for deep submicron semiconductor device simulator
abstract
A particle simulation method is introduced in which two kinds of particle models are used in one device. A conventional Monte Carlo particle model is used in the region where nonstatic effects are evident, and a particle model based on Langevin's equation is used in the region where the drift-diffusion approximation is valid. In this way it is possible to obtain efficiency and the required physical accuracy in device simulation. For the validity of this scheme, a silicon n/sup +/-n-n/sup +/ structure is simulated, and some important results are presented.>
Gyo-Young Jin, Young-June Park, Hong-Shick Min
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2