Abstract Three parallel implementations of a divide‐and‐conquer search algorithm (called SUDA2) for finding minimal unique itemsets (MUIs) are compared in this paper. The identification of MUIs is used by national statistics agencies for statistical disclosure assessment. The first parallel implementation adapts SUDA2 to a symmetric multi‐processor cluster using the message passing interface (MPI), which we call an MPI cluster; the second optimizes the code for the Cray MTA2 (a shared‐memory, multi‐threaded architecture) and the third uses a heterogeneous ‘group’ of workstations connected by LAN. Each implementation considers the parallel structure of SUDA2, and how the subsearch computation times and sequence of subsearches affect load balancing. All three approaches scale with the number of processors, enabling SUDA2 to handle larger problems than before. For example, the MPI implementation is able to achieve nearly two orders of magnitude improvement with 132 processors. Performance results are given for a number of data sets. Copyright © 2009 John Wiley & Sons, Ltd.

The PerCo performance control framework is capable of managing the distributed execution of scientific coupled models using migration, for example, in response to changes in an execution environment. PerCo monitors execution times and reacts according to an adaptive performance control strategy whenever serious changes of behaviour occur. A computationally cheap technique is used per model to smooth the series of monitored execution times and to provide a short-term forecast for future execution times on currently assigned resources. Where this short-term forecast fails to be achieved, the system analyses whether migration would improve matters. For models that are candidates for migration, more accurate but computationally expensive techniques are used to form a longer-term prediction of future execution times on various candidate resources. Based on the predicted gain, a migration decision is made taking account of the expected cost of migration. Experimental results for small real scientific coupled models show that the performance control strategy behaves effectively in scenarios in which the ambient load is varied during execution.

Working Group on Automatic Performance Analysis (APART)This special issue is devoted to research undertaken by the European-American Working Group on Automatic Performance Analysis (APART).APART (http://www.fz-juelich.de/apart)was established in 1999 as an EU-funded working group with more than 15 partners from Europe and the U.S.A., plus more than 10 associate partners from academia

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Abstract In recent years, there has been increasing interest in the development of computer simulations of complex biological systems, and of multi‐physics and multi‐scale physical phenomena. Applications have been developed that involve the coupling together of separate executable models of individual systems, where these models may have been developed in isolation. A lightweight yet general solution is required to problems of linking coupled models, and of handling the incompatibilities between interacting models that arise from their diverse origins and natures. Many such models require high‐performance computers to provide acceptable execution times, and there is increasing interest in utilizing Grid technologies. However, Grid applications need the ability to cope with heterogeneous and dynamically changing execution environments, particularly where run‐time changes can affect application performance. A general coupling framework (GCF) is described that allows the construction of flexible coupled models. This approach results in a component‐based implementation of a coupled model application. A semi‐formal presentation of GCF is given. Components under GCF are separately deployable and coupled by simple data flows, making them appropriate structures for dynamic execution platforms such as the Grid. The design and initial implementation of a performance control system (PERCO) is reviewed. PERCO acts by redeploying components, and is thus appropriate for controlling GCF coupled model applications. Redeployment decisions in PERCO require performance prediction capabilities. A proof‐of‐concept performance prediction algorithm is presented, based on the descriptions of GCF and PERCO. Copyright © 2005 John Wiley & Sons, Ltd.

Abstract OOLALA is an object‐oriented linear algebra library designed to reduce the effort of software development and maintenance. In contrast with traditional (Fortran‐based) libraries, it provides two high abstraction levels that significantly reduce the number of implementations necessary for particular linear algebra operations. Initial performance evaluations of a Java implementation of OOLALA show that the two high abstraction levels are not competitive with the low abstraction level of traditional libraries. These initial performance results motivate the present contribution—the characterization of a set of storage formats (data structures) and matrix properties (special features) for which implementations at the two high abstraction levels can be transformed into implementations at the low (more efficient) abstraction level. Copyright © 2005 John Wiley & Sons, Ltd.

Abstract The Java language specification states that every access to an array needs to be within the bounds of that array, i.e. between 0 and array length − 1. Different techniques for different programming languages have been proposed to eliminate explicit bounds checks. Some of these techniques are implemented in off‐the‐shelf Java Virtual Machines (JVMs). The underlying principle of these techniques is that bounds checks can be removed when a JVM/compiler has enough information to guarantee that a sequence of accesses (e.g. inside a for‐loop) is safe (within the bounds). Most of the techniques for the elimination of array bounds checks have been developed for programming languages that do not support multi‐threading and/or enable dynamic class loading. These two characteristics make most of these techniques unsuitable for Java. Techniques developed specifically for Java have not addressed the elimination of array bounds checks in the presence of indirection; that is, when the index is stored in another array (indirection array). With the objective of optimizing applications with array indirection, this paper proposes and evaluates three implementation strategies, each implemented as a Java class. The classes provide the functionality of Java arrays of type int so that objects of the classes can be used instead of indirection arrays. Each strategy enables JVMs, when examining only one of these classes at a time, to obtain enough information to remove array bounds checks. Copyright © 2005 John Wiley & Sons, Ltd.

In this paper we review the design of a sequential object oriented linear algebra library, OOLALA. Several designs are proposed and used to classify existing sequential object oriented libraries. The classification is based on the way that matrices and matrix operations are represented. OOLALA's representation of matrices is capable of dealing with certain matrix operations that, although mathematically valid, are not handled correctly by existing libraries. OOLALA also enables implementations of matrix calculations at various abstraction levels ranging from the relatively low-level abstraction of a Fortran BLAS-like implementation to higher-level abstractions that hide many implementation details. OOLALA addresses a wide range of numerical linear algebra functionality while the reviewed object oriented libraries concen trate on parts of such functionality. We include some preliminary performance results for a Java implementation of OOLALA.

An experimental study of four different schemes for parallelisation of FORTRAN codes is presented.One scheme is manual (performed by the programmer), the other three are automatic (performed entirely by software).The performance of code generated for two parallel computers from seven different test cases is compared, and reasons for differences in achieved performance between the four parallelisation schemes are analysed.It is concluded that, even using sophisticated techniques, high performance parallelised code cannot be generated by automatic tools unless they take into account feedback about execution-time behaviour.Both post-execution performance analysis and interaction with the programmer are necessary for success.This observation argues for user-centred, feedback-driven parallelisation tools that aid the manual process.

This paper presents an overview of the activities carried out within the ESPRIT project OCEANS whose objective is to investigate and develop advanced compiler infrastructure for embedded VLIW processors. This combines high and low-level optimisation approaches within an iterative framework for compilation. These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Article Free Access Share on Performance improvement through overhead analysis: a case study in molecular dynamics Authors: Graham D. Riley Centre for Novel Computing, University of Manchester, Oxford Road, Manchester M13 9PL, United Kingdom Centre for Novel Computing, University of Manchester, Oxford Road, Manchester M13 9PL, United KingdomView Profile , J. Mark Bull Centre for Novel Computing, University of Manchester, Oxford Road, Manchester M13 9PL, United Kingdom Centre for Novel Computing, University of Manchester, Oxford Road, Manchester M13 9PL, United KingdomView Profile , John R. Gurd Centre for Novel Computing, University of Manchester, Oxford Road, Manchester M13 9PL, United Kingdom Centre for Novel Computing, University of Manchester, Oxford Road, Manchester M13 9PL, United KingdomView Profile Authors Info & Claims ICS '97: Proceedings of the 11th international conference on SupercomputingJuly 1997 Pages 36–43https://doi.org/10.1145/263580.263589Published:11 July 1997Publication History 12citation261DownloadsMetricsTotal Citations12Total Downloads261Last 12 Months6Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Parallelising compilers typically need some performance estimation capability in order to evaluate the trade-offs between different transformations. Such a capability requires sophisticated techniques for analysing the program and providing quantitative estimates to the compiler's internal cost model. Making use of techniques for symbolic evaluation of the number of iterations in a loop, this paper describes a novel compile-time scheme for partitioning loop nests in such a way that load imbalance is minimised. The scheme is based on a property of the class of canonical loop nests, namely that, upon partitioning into essentially equal-sized partitions along the index of the outermost loop, these can be combined in such a way as to achieve a balanced distribution of the computational load in the loop nest as-a-whole. A technique for handling non-canonical loop nests is also presented; essentially, this makes it possible to create a load-balanced partition for any loop nest which consists of loops whose bounds are linear functions of the loop indices. Experimental results on a virtual shared memory parallel computer demonstrate that the proposed scheme can achieve better performance than other compile-time schemes.

Massively parallel programs generally use memory on a vast scale, compared with sequential programs. Indeed, performance seems to 'trade-off' against memory use. Hence, regulation of memory use, via control of the workload, is a fundamental requirement in a massively parallel computer system. Moreover, this must be achieved with a minimum of disruption to the performance of its massively parallel computations. This paper investigates how this has been achieved in the Manchester Data-Flow Computing System, which is based on an experimental, fine-grain massively parallel computer architecture that has been extensively developed over the last fifteen years. The design and performance of the Throttle Unit, which is the device responsible for managing the workload in this system, are presented and analysed.

The Manchester Data-Flow Machine, MDFM, has evolved continuously during the past decade. By the time the prototype uniprocessor hardware system was decommissioned, in 1989, the putative multi-processor architecture comprised separate Processing Elements and Structure Store Units, together with a “global” Allocator and Throttle Unit, all linked by a packet-based Interconnection Switch.

The authors investigate the nature and extent of the benefits and adverse effects of iterative instructions in the prototype Manchester Dataflow Computer. Iterative instructions are shown to be highly beneficial in terms of the number of instructions executed and the number of tokens transferred between modules during a program run. This benefit is apparent at hardware level, giving significantly reduced program execution times. However, the full benefits are not realized due to interference between lengthy iterative instructions. It is suggested that restructuring of buffers and the function unit array in the prototype hardware configuration can reduce this interference. Other possibilities for improvement are suggested. For example, the slowdown effect observed in hardware speedup curves could be tackled by treating iterative instructions differently from fine-grain instructions. An alternative structure for the processing element in which certain function units are specialized for executing iterative instructions is being investigated in this connection.>

A design for a highly parallel data structure store for the prototype Manchester Dataflow Computer is presented. The main design objective is to allow all storage functions to be performed concurrently. The functions include space allocation and garbage collection, as well as operations for reading and writing the store. The resulting design is scalable in that an incremental increase in performance for any function can be achieved by adding appropriate hardware modules into the system. A relative balance in performance between the different functions can therefore be achieved. In the hardware structure store, the logical and the physical function units are designed separately. This increases flexibility for configuring multiprocessor dataflow systems. A single hardware module performing all the functions has been constructed and attached to the prototype Manchester Dataflow Machine. The performance of this configuration is discussed.