Photonic networks based on wavelength division multiplexing (WDM) and optical path technologies are expected to realize flexible, transparent, and cost-effective transport networks with a large transmission capacity. This paper explores the design framework of photonic transport networks taking into consideration the operation administration and maintenance (OA&M) functions required for the successful introduction of WDM systems based on the optical path concept. From the view point of network maintenance, clear distinction is made between the optical path layer and the optical section layer to facilitate accurate and smooth failure localization. The digital multiplexing span between physical multiplexing interfaces at the end-to-end digital nodes should have the same maintenance span as the corresponding optical path. We argue that cooperative maintenance by OA&M functions at both the digital and optical layers can be a practical way of network supervision. A supervisory (SV) signal transfer method and a configuration that is suitable for the terrestrial trunk network are also indicated. As an example, a practical SV system design methodology and an actual procedure developed for a single channel optical transmission system based on optical in-line amplifiers are introduced. Furthermore, application of the developed SV system and network restoration schemes is discussed for future WDM-based photonic networks. The OA&M aspects introduced will be valuable for creating future photonic network systems.

High-quality speech codec modules operating at 16 and 8 kb/s have been developed using an adaptive predictive coding with adaptive bit allocation (APC-AB) scheme. An optimized APC-AB algorithm is studied that reduces processing complexity while maintaining speech quality. The coding algorithm is implemented in two digital signal processors (DSPs). The DSP chips, a framing LSI circuit, a PCM codec, and some peripheral ICs are integrated in each of two compact packages, i.e. codec modules, operating at 16 or 8 kb/s. The codec module size is as small as 80 mm*50 mm*12 mm, and its typical power consumption is 500 mW using 2- mu m CMOS LSI technology. At 16 kb/s this APC-AB codec achieves high speech quality, close to that of a 7-bit mu -law PCM. The codec modules are expected to be used for various applications such as customer premises multiplexers for digital leased lines, digital mobile radio, and stored-and-forward-message systems (voice-mail systems).>

An adaptive predictive coding with dynamic quantization adjustment(APC-DQA) is proposed for speech coding at 16 kbits/s, which aims to reduce processing delay and hardware complexity, while attaining "toll quality". The proposed scheme utilizes time-domain processing to lessen the processing delay. Moreover, it employs backward processing in both prediction and quantization, which requires less side information than forward processing. It also incorporates adaptive bit allocation in sub-intervals of each frame so as to remove redundancies due to periodic concentration of the prediction residual energy. The performance evaluation results show that the processing delay of the APC-DQA is 2/3 that of an adaptive predictive coding with adaptive bit allocation scheme (APC-AB) [1]. Moreover, its hardware complexity is approximately 70% to 80% of the APC-AB. It was also shown that this scheme can provide speech quality subjectively equivalent to 6.6 bit Log-PCM.

Recently much intensive research of 16kbps Speech coding algorithm has been conducted aiming to reduce the transmission bit rate and yet provides high speech quality. Adaptive predictive coding with adaptive bit allocation (APC-AB)[1] is considered to be one promising approach. However, the processing of this coding algorithm is so complicated that the implementation of the algorithm on a general-purpose signal processor, especially if fixed-point arithmetic DSPs are used, requires careful study of arithmetic operation precision and same way to reduce the number of processing cycles. Taking account of these points, real-time signal processing using a fixed-point signal processing chip (FDSP-3) has been studied, and a prototype codec has been realized. The prototype codec satisfied the CCITT mask of signal-to-total distortion ratio for PCM codecs and showed quality good enough for "toll" speech.