Physical Unclonable Functions (PUFs) are a very useful resource in cryptography with many applications ranging from system authentication to secret key generation. Side-channel attacks (SCAs) are a major concern in any physical implementation of a cryptographic module, and PUFs are no exception. Electromagnetic (EM) leakage from the implementation of a ring-oscillator-based PUF (RO-PUF) can be exploited to retrieve sensitive information that compromises the security of the cryptographic scheme incorporating the PUF. In this paper, we analyse the EM leakage of an RO-PUF implemented on FPGA, highlight its main vulnerabilities, and propose alternative countermeasures and architectures to mitigate the threat of this type of attack. Furthermore, we evaluate the cost in terms of area overhead of the proposed implementations compared to the original design.

The development of hardware countermeasures against hardware attacks has attracted the attention of the scientific community over the past two decades. Side-Channel Analysis (SCA) and Fault Injection Attacks (FIA) represent a significant risk to the security of cryptographic circuits. Combined countermeasures against these types of attack must be carefully designed if both protections are required in the same implementation without interfering with the other. In this paper, a combined proposal is presented to counteract the SCA and FIA attacks. SCA countermeasures are based on a low-entropy masking scheme, while the FIA countermeasure is based on a signature generator detection scheme. Both have been experimentally implemented in an AES cipher in FPGA. Experimental FIA attacks, first-order Correlation Power Analysis (CPA) attacks, and Test Vector Leakage Assessment (TVLA) tests have been carried out to evaluate the improvement in the security levels. The experimental results show that for an increase in area 28.77% and a frequency degradation of 4.05% with respect to the unprotected implementation, the protected Advanced Encryption Standard (AES) scheme shows great security metrics against FIA (99.87% fault coverage) and SCA attacks.

Fault injection, in particular Differential Fault Analysis (DFA), has become one of the main methods for exploiting vulnerabilities into the block ciphers currently used in a multitude of applications. In order to minimize this type of vulnerabilities, several mechanisms have been proposed to detect this type of attacks. However, these mechanisms can have a significant cost or not adequately cover the implementations against fault attacks. In this paper a novel approach is proposed, consisting in generating the signatures of the internal state using a Hamming code. This allows to cover a larger amount of faults allowing to detect even or odd bit changes, as well as multi-bit and multi-byte changes, the ones that make ciphers more vulnerable to DFA attacks. As case of study, this approach has been applied to the Advanced Encryption Standard (AES) block cipher implemented on FPGA using T-boxes. The results suggest a higher fault coverage with an overhead of 16% of resource consumption and without any penalty in the frequency degradation.

The design of near future cryptocircuits will require greater performance characteristics in order to be implemented in devices with very limited resources for secure applications. Considering the security against differential power side-channel attacks (DPA), explorations of different implementations of dual-precharge logic gates with advanced and emerging technologies, using nanometric FinFET and Tunnel FET transistors, are proposed aiming to maintain or even improve the security levels obtained by current Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) technologies and reducing the resources needed for the implementations. As case study, dual-precharge logic primitives have been designed and included in the 4-bit substitution box of PRIDE algorithm, measuring the performance and evaluating the security through simulation-based Differential Power Analysis (DPA) attacks for each implementation. Extensive electrical simulations with predictive Predictive Transistor model on scaled 16nm and 22nm MOSFET, 16nm and 20nm FinFET, and 20nm Tunnel Field Effect Transistor (TFET) demonstrate a clear evolution of security and performances with respect to current 90nm MOSFET implementations, providing FinFET as fastest solutions with a delay 3.7 times better than conventional proposals, but TFET being the best candidate for future cryptocircuits in terms of average power consumption (x0.02 times compared with conventional technologies) and security in some orders of magnitude.

In this paper, a Differential Power Analysis (DPA) vulnerability analysis on Trivium stream cipher is presented. Compared to the two previously presented DPA attacks on Trivium, we retrieve the whole key without making any hypothesis during the attack. An optimized power model is proposed allowing the power trace acquisition without making any algorithmic-noise removement thus simplifying the attack strategy considerably. The theoretical vulnerability analysis is presented and then checked developing a simulation-based DPA attack on a standard CMOS Trivium implementation in a 90nm TSMC technology. The results show that our attack is successful for random keys, saving in computer resources and time respecting to previously-reported attacks. The attack is independent on technology used for the implementation of Trivium and can be used to measure the security of novel Trivium implementations.

Information leakaged by cryptosistems can be used by third parties to reveal critical information using Side Channel Attacks (SCAs). Differential Power Analysis (DPA) is a SCA that uses the power consumption dependence on the processed data. Designers widely use differential logic styles with constant power consumption to protect devices against DPA. However, the right use of such circuits needs a fully symmetric structure and layout, and to remove any memory effect that could leak information. In this paper we propose improved low-power gates that provide excellent results against DPA attacks. Simulation based DPA attacks on Sbox9 are used to validate the effectiveness of the proposals.

Clock Gating (CG) is a well known technique to reduce dynamic power consumption by stopping the clock to avoid unnecessary transitions in synchronous circuits. The abilities of different CG-styles to save power at a flip-flop level, depending on the input activity, are analysed in this paper. Also, since conventional CG techniques usually do not take into account leakage power, some optimization procedures and guidelines are presented for leakage reduction. Focusing on those structures that do not need a latch to remove undesired transitions in gated clock, a leakage value of a fourth of the original one is achieved without degradation in timing performances.

This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asychronous address-event representation (AER) communication framework and was developed in the context of a European Union funded project. It has four custom mixed-signal AER chips, five custom digital AER interface components, 45k neurons (spiking cells), up to 5M synapses, performs 12G synaptic operations per second, and achieves millisecond object recognition and tracking latencies.

We present a neuromorphic fully digital convolution microchip for Address Event Representation (AER) spike-based processing systems. This microchip computes 2-D convolutions with a programmable kernel in real time. It operates on a pixel array of size 32 x 32, and the kernel is programmable and can be of arbitrary shape and size up to 32 x 32 pixels. The chip receives and generates data in AER format, which is asynchronous and digital. The paper describes the architecture of the chip, the test setup, and experimental results obtained from a fabricated prototype.

In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques. The convolution processing is based on the address–event-representation (AER) technique, which is a spike-based biologically inspired image and video representation technique that favors communication bandwidth for pixels with more information. As a first test prototype, a pixel array of 16$\,\times\,$16 has been implemented with programmable kernel size of up to 16$\, \times\,$16. The chip has been fabricated in a standard 0.35-${\mu }$m complimentary metal–oxide–semiconductor (CMOS) process. The technique also allows to process larger size images by assembling 2-D arrays of such chips. Pixel operation exploits low-power mixed analog–digital circuit techniques. Because of the low currents involved (down tonanoamperesor evenpicoamperes), an important amount of pixel area is devoted to mismatch calibration. The rest of the chip uses digital circuit techniques, both synchronous and asynchronous. The fabricated chip has been thoroughly tested, both at the pixel level and at the system level. Specific computer interfaces have been developed for generating AER streams from conventional computers and feeding them as inputs to the convolution chip, and for grabbing AER streams coming out of the convolution chip and storing and analyzing them on computers. Extensive experimental results are provided. At the end of this paper, we pro

One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation and distribution tree. This paper analyzes how the use of an asymmetric clock can be an important solution to reduce the switching noise generated by the global clock, with a very reduced degradation in performances and reliability. The suited sizing of clock generators and the design of asymmetric clock tree cells, show the benefits of the proposed technique, validated through a design example where a 50% of noise reduction is achieved with 10% of loss in operation frequency and no penalty, even saving, in power consumption.

This work proposes the usage of staggered initialization schemes in digital sequential circuits as complementary technique to reduce the simultaneous switching activity, pursuing the minimization of switching noise levels. Simultaneous switching noise (SSN) generation has been evaluated in digital sequential circuits during initialization and a general synthesis methodology has been proposed in order to implement the staggered initialization schemes at system level. The evaluation of this methodology was made with counter arrays using 0.35μm AMS library cells. In addition, timing considerations, clock suppression during initialization cycles, and the type of cell chosen to implement the staggered distribution are discussed. Main results include noise reduction levels, by suppression of power supply fluctuations, up to 66.7% in post-layout simulations when using staggered techniques enhanced with clock gating during initialization.

In this paper we briefly summarize the fundamental properties of spike events processing applied to artificial vision systems. This sensing and processing technology is capable of very high speed throughput, because it does not rely on sensing and processing sequences of frames, and because it allows for complex hierarchically structured cortical-like layers for sophisticated processing. The paper includes a few examples that have demonstrated the potential of this technology for high-speed vision processing, such as a multilayer event processing network of 5 sequential cortical-like layers, and a recognition system capable of discriminating propellers of different shape rotating at 5000 revolutions per second (300000 revolutions per minute).

A high speed sample image processing application using AER-based components is presented. The setup objective is to distinguish between two propellers of different shape rotating at high speed (around 1000 revolutions/sec) to show event-based systems capabilities in high speed applications. Event-based schemes allow the most relevant information to propagate faster through the system layers. So image processing is sped up because a rough result may be available when only a little part of the input has arrived. This setup is much faster than the conventional frame-based image processing systems because they would need to process more than 10kFrames/s to do the same task proposed here, whereas only few events are required with the event based technique

A chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. This is a first prototype of reduced size (16 times 16 pixels) to validate system level techniques. It has been fabricated in AMS-0.35 mum, 2-poly, 3-metal technology. Chip inputs and outputs are coded using address event representation (AER). This is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge numbers of pixels located on different chips. Pixels generate 'events' according to their activity levels. More active pixels generate more events per unit time and access the interchip communication channel more frequently, whereas pixels with low activity consume less communication bandwidth. This allows communicating more relevant information in a very short time. Specific PCI boards have been developed to feed images into the chip and to read images out of it

A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the address-event- representation (AER) is demonstrated. The system includes a retina chip, two convolution chips, a 2D winner-take-all chip, a delay line chip, a learning classifier chip, and a set of PCBs for computer interfacing and address space remappings. The components use a mixture of analog and digital computation and will learn to classify trajectories of a moving object. A complete experimental setup and measurements results are shown.

The application of design reuse to analog and mixed-signal components for System-on-Chip (SoC) is an emerging and revolutionary field. This paper presents a methodological approach to this area illustrated with a mixed-signal case study.

This paper presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm is intended for including the inertial and degradation delay models. Simulation results are very similar to those obtained by electrical simulators, and show a higher accuracy compared to conventional delay models implemented in current logic simulators.

This paper proposes a methodology for designing sampled-data mixed-signal circuits by using VHDL-based behavioural descriptions. The goal is using a VHDL description of both the analog and the digital part, to simulate and verify the entire mixed-signal system, as well as to facilitate the synthesis and fault simulation of the digital part. As an example of the proposed methodology, a digitally corrected/calibrated pipeline A/D converter (ADC) has been designed. Among other aspects of general interest, we show how analog dynamic effects are incorporated in order to obtain accurate high level simulations. Results from simulations carried out using QuickHDL in MentorGraphics prove the feasibility of the approach and are in agreement with those obtained experimentally from a silicon prototype.

The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the degradation delay model presented in previous papers with a new algorithm to handle the inertial effect, and is able to take account of the propagation and filtering of arbitrarily narrow pulses (glitches, etc.). The model clearly overcomes the limitations of conventional approaches.

This paper proposes a behavioural model for digitally corrected/calibrated pipeline A/D converters (ADCs) based on standard VHDL. We will show how VHDL-based analog modelling can be efficiently used to simulate and verify the functionality of these mixed-signal systems where significant interaction exists between analog and digital parts. The main motivation for describing the behavioural model (analog and digital) directly in standard VHDL is to make possible the synthesis and fault simulation of the digital part using standard digital tools. Results from simulations carried out using QuickHDL in Mentor-Graphics prove the feasibility of the approach and are in agreement with those obtained experimentally from a Silicon prototype.

This communication presents a self-timed scan-path architecture, to be used in a conventional synchronous environment, and with basic application in digital testing in a Smart-Substrate MCM. Three different self-timed asynchronous scan cells are proposed (Sense, Drive and Drive and Sense cells) that can be connected to form a self-timed scan-path. The main advantage is that no global test clock is needed, avoiding clock skew and synchronization faults in test mode.

The purpose of this paper is to present a novel modular N-user asynchronous arbiter circuit which is insensitive to metastable operation (i.e., the new arbiter cannot fail because of metastability), operating asynchronously and incorporating a modular architecture. A 1.5 /spl mu/m CMOS prototype arbiter has been designed and tested. Laboratory tests demonstrate the arbiter operates correctly.