By moving data and computation away from the end user to more powerful servers in the cloud or to cloudlets at the edge, end user devices only need to compute locally for small amounts of data and when low latency is required. However, with the advent of 6G and Internet-of-Everything, the demand for more powerful networks continues to grow. The introduction of Software-Defined Networking and Network Function Virtualization has allowed us to rethink networks and use them for more than just routing data to servers. In addition, the use of more powerful network devices is bringing new life to the concept of active networks in the form of in-network computing. In-Network Computing provides the ability to move applications into the network and process data on programmable network devices as they are transmitted. In this work, we provide an overview of in-network computing and its enabling technologies. We take a look at the programmability and different hardware architectures for SmartNICs and switches, focusing primarily on accelerators such as FPGAs. We discuss the state of the art and challenges in this area, and look at CGRAs, a class of hardware accelerators that have not been widely discussed in this context.

We present a way of failure detection in real-time unmanned aerial vehicles (UAVs) by integrating Chaos Theory and AI techniques on an FPGA board. The Signal Analysis based on Chaos using the Density of Maxima (SAC-DM) validates the input of the Machine Learning (ML) model due to the relation between the density of maxima and autocorrelation length. While the accuracies achieved solely by SAC-DM are not remarkably high, the ML model demonstrates an accuracy of 92.46% when utilizing sac-dm results as inputs. The unprecedented integration of SAC-DM on FPGA board serves as a solution for high-speed onboard processing, parallel integrated data synchronization and fusion, and an enhanced low-power architecture.

Networks-on-Chip (NoCs) are beneficial for reconfigurable systems that require a high degree of parallel and scalable communication. NoCs are reusable as hardware accelerators can be exchanged via dynamic partial reconfiguration. Nevertheless, NoCs are not conceptualized for the use in a virtualized environment where applications from multiple virtual machines have to share reconfigurable resources. Many state-of-the-art works assign hardware accelerators exclusively to a single virtual machine, which limits the number of processed hardware tasks and leads to underutilization of FPGA area. Therefore, we provide a NoC virtualization layer that allows the execution of several pipelined hardware tasks agnostic of the location of the required hardware accelerators. The allocation of tasks to processing elements can be adapted to dynamically changing requirements, while unauthorized access is prohibited. Further, we provide a scheduler that schedules hardware tasks in spatial and temporal respect to processing elements in the NoC. The proposed heuristic considers task priorities, a possible reuse of accelerators and hop counts. In over-load conditions, the tasks with the lowest priorities are postponed. Our virtualization layer increases the number of tasks processed by 22.6% compared to an approach that grants exclusive access.

The amount of image data to be processed has increased tremendously over the last decades. One major computer vision task is the extraction of information to find patterns in and between images. One well-studied pattern recognition algorithm is AKAZE which builds a nonlinear scale space to detect features. While being more efficient compared to its predecessor KAZE, the computational demands of AKAZE are still high. Since many real-world computer vision applications require fast computations, sometimes under hard power and time constraints, FPGAs became a focus as a suitable target platform. This work presents a highly modularized and parameterizable implementation of the AKAZE feature detection algorithm integrated into HiFlipVX, which is a High-Level Synthesis library based on the OpenVX standard. The fine granular modularization and the generic design of the implemented functions allows them to be easily reused, increasing the workflow for other computer vision algorithms. The high degree of parameterization and extension of the library enables also a fast and extensive exploration of the design space. The proposed design achieved a high repeatability and frame rate of up to 480 frames per second for an image resolution of 1920×1080 compared to related work.

This paper presents a novel system for accurate placement of pedicle screws. The system consists of a new light-weight (<10 kg), kinematically redundant, and fully torque controlled robot. Additionally, the pose of the robot tool-center point is tracked by an optical navigation system, serving as an external reference source. Therefore, it is possible to measure and to compensate deviations between the intraoperative and the preoperatively planned pose. The robotic arm itself is impedance controlled. This allows for a new intuitive man-machine-interface as the joint units are equipped with torque sensors: the robot can be moved just by pulling/pushing its structure. The surgeon has full control of the robot at every step of the intervention. The hand-eye-coordination problems known from manual pedicle screw placement can be omitted

In the robotic community more and more hands have been developed. These newly designed manipulators greatly outperform their ancestors in terms of available sensor signals, applicable grasping force, mechanical stability, reliability, kinematic design and more. This development extends the possible range and complexity of applications of robotic grippers also to areas outside of well structured laboratories and simple tasks. It also calls for more flexible control structures to provide a framework for implementing and executing these newly arising tasks without having to start from scratch for each new task. During the last few years we developed a control system architecture for DLR hand II that proved to be useful for a great variety of different applications. This paper presents the basic ideas behind DLR hand II's hard- and software architecture adapted to new needs in data processing.