Spiking neural networks (SNNs) can improve inference accuracy through joint optimization of synaptic weights and neuronal thresholds. However, mixed-signal neuromorphic processors, which are designed for energy efficiency using analog circuits, face practical limitations. In particular, digital to analog converters (DACs) often lack sufficient resolution to represent the large threshold values required by joint optimization. To address this issue, we propose a mixed-signal neuromorphic processor architecture that shifts threshold control to digital logic. This approach removes the need for high-resolution DACs and allows dynamic threshold adjustment without modifying the analog neural core. We also propose a learning method tailored to this architecture. We evaluate the proposed design on five image classification benchmarks, measuring accuracy, latency, and energy consumption. The results show that our architecture consistently improves accuracy across benchmarks while incurring only minimal latency and energy overhead. This demonstrates that the proven benefits of joint weight and threshold learning can be realized in energy efficient analog hardware.

This study presents a practically deployable anti-spoofing system for fingerprint biometrics based on electric finger channel response (FCR) to detect falsification attempts using artificial fake fingerprints. Meanwhile, electric signals passed through the human body are particularly vulnerable to distortion from electromagnetic interference (EMI) induced into the body channel by the body antenna effects. The proposed EMI-robust fake fingerprint detection (FFD) employed a neural fully-connected filter trained on the proposed detection features extracted from the amplitude variation and time dispersion characteristics of FCR. A valid FCR dataset for feature analysis was acquired using custom-developed devices in a designated experimental setup involving 20 subjects. Following compatibility verification of the FCR-based FFD with a capacitive-sensing fingerprint scanner in the implemented prototype, the performance evaluation under onsite EMI conditions—primarily modeled as wide-band pulsed-radiated emission and narrow-band sinusoidal wave interferences—showed that the proposed FFD achieved false rejection and acceptance rates of 0.9$\%$and 0.5$\%$, respectively.

Developing low-power neuromorphic processors capable of inferring outcomes from SNN Frameworks presents significant challenges, largely due to the gap between frameworks and analog circuit-based SNNs. This paper analyzes the root of this gap as stemming from over/underflow issues and proposes mixed-signal neurons as a solution, further developing a neural core composed of these neurons. In the development of the neural core, we incorporate a design methodology for application-specific neural core optimization. We advance to develop a neural engine as an independent IP, ultimately introducing the snnTorch Architecture (STARC), an integrated mixed-signal neuromorphic processor architecture. The STARC processor, developed as a prototype, demonstrates operational correctness and exceptional low-power performance.

This study presents a highly reliable approach to prevent fingerprint spoofing attacks based on electric body pulse responses (BPRs) in personal Internet of Things (IoT) gadgets. Real fingerprint pulse response (RFPR) and fake fingerprint pulse response (FFPR) data were collected from ten subjects for four weeks. The FFPR was obtained by wearing a fake fingerprint made of artificial substances, such as conductive silicone, over the finger. We analyzed different patterns of FFPR compared to RFPR using an electric circuit model of the proposed fingerprint anti-spoofing system based on BPRs. Simple features comprising ten, five, or three datapoints were selected by the minimum redundancy maximum relevance (MRMR) algorithm and led to reduction in processing complexity. We also validated its robustness to sampling offset errors caused by practical sampling operations in devices based on the evaluation of classification accuracy using machine learning algorithms, such as${k}$-nearest neighbor (KNN) and support vector machine (SVM). Finally, the effectiveness of the selected feature was evaluated using unsupervised anomaly detection algorithms, such as principal component analysis (PCA), one-class SVM (OC-SVM), and variational autoencoder (VAE), in a practical scenario with sampling offset errors in the training and test data. The VAE outperformed PCA and OC-SVM by achieving a detection accuracy of 99.76% using raw data under 100 datapoints and 97.60% with reduced features having only five datapoints, regardless of sampling offset errors. Therefore, the proposed anomaly detection system based on EPRs can provide promising fingerprint spoof detection in IoT devices with limited computing resources.

Ranging from circuit-level characterization to designing a platform architecture, developing a design automation tool, and fabricating a System on Chip (SoC), this article deals with the entire development process for ultralow-power (ULP) SoCs for Internet-of-Things (IoT) end nodes. More precisely, this article first focuses on the unique characteristics of the ULP circuits, the temperature effect inversion (TEI), i.e., the delay of the ULP circuits decreases with increasing temperature. Existing TEI-aware low-power (TEI-LP) techniques have incredible potential to further reduce the power consumption of conventional ULP SoCs, but there is a critical limitation to be widely adopted in real SoCs. To address this limitation and realize the ULP SoCs that can fully benefit from the TEI-LP techniques, this article proposes a new TEI-inspired SoC platform (TIP) architecture. On top of that, taking into account that the highly complex, time consuming, and labor-intensive development process of these ULP SoCs may hinder their widespread use for IoT end nodes, this article presents a new electronic design automation tool to accelerate ULP SoC development, RISC-V express (RVX). Finally, by using the RVX, this article introduces a TIP prototyping chip fabricated in 28-nm FD-SOI technology. This chip demonstrates that power savings of up to 35% can be achieved by lowering the supply voltage from 0.54 to 0.48 V at 25 °C and 0.44 V at 80 °C while continuing to operate at a target 50-MHz clock frequency.

A novel low power SoC bus with low-leakage and low swing technique is proposed. The repeater used in the bus lines effectively reduces leakage power through stacking effect, not losing its logic values even in sleep mode. The proposed SoC bus reduces not only the leakage power in the normal active/sleep mode but also both dynamic and leakage power in the low swing operation mode. The proposed scheme reduces the total power by 44.5% compared to the conventional SoC bus architecture.

A high performance and low power clock delayed sleep mode (CDSM) domino logic is proposed for wide fan-in domino logic. The CDSM-domino logic not only improves the robustness but also reduces the active and stand-by power. The proposed scheme reduces delay by 21%, dynamic power by 16%, and leakage power by 91% respectively compared to the typical wide fan-in domino logic in 0.18? CMOS technology. In addition, the sleep mode entrance power is reduced to 10-5 of the HS-domino logic [3].