Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.

Rahul Jain 0004

dblp:42/4430-4 · DBLP profile ↗
← Back
4ranked-venue papers
4as first author
0since 2021 · last 2017
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 56% Parallel and multicore computing · 28% Energy-efficient computing · 17%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache
0.312017
Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network · ACM Trans. Archit. Code Optim. 2017
Memory systems › cache management › cache partitioning
last-level cache partitioning
0.312017
Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network · ACM Trans. Archit. Code Optim. 2017
Parallel and multicore computing › multiprocessor system
multicore resource management
0.312017
Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network · ACM Trans. Archit. Code Optim. 2017
Energy-efficient computing › power management
dynamic voltage and frequency scaling
0.112017
Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network · ACM Trans. Archit. Code Optim. 2017
Energy-efficient computing
power management
0.112017
Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network · ACM Trans. Archit. Code Optim. 2017

Methods — techniques the papers use, named apart from their topics

online reinforcement learning · 0.3cooperative multi-agent reinforcement learning · 0.3
YearPublicationVenuePosition
2017 A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning
abstract
The widening gap between the processor and memory performance has led to the inclusion of multiple levels of caches in the modern multi-core systems. Processors with simultaneous multithreading (SMT) support multiple hardware threads on the same physical core, which results in shared private caches. Any inefficiency in the cache hierarchy can negatively impact the system performance and motivates the need to perform a co-optimization of multiple cache levels by trading off individual application throughput for better system throughput and energy-delay-product (EDP). We propose a novel coordinated multiagent reinforcement learning technique for performing Dynamic Cache Co-partitioning, called Machine Learned Caches (MLC). MLC has low implementation overhead and does not require any special hardware data profilers. We have validated our proposal with 15 8-core workloads created using Spec2006 benchmarks and found it to be an effective co-partitioning technique. MLC exhibited system throughput and EDP improvements of up to 14% (gmean:9.35%) and 19.2% (gmean: 13.5%) respectively. We believe this is the first attempt at addressing the problem of multi-level cache co-partitioning.
Rahul Jain 0004, Preeti Ranjan Panda, Sreenivas Subramoney
DATE1
2017 Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network
abstract
Modern multi-core systems provide huge computational capabilities, which can be used to run multiple processes concurrently. To achieve the best possible performance within limited power budgets, the various system resources need to be allocated effectively. Any mismatch between runtime resource requirement and allocation leads to a sub-optimal energy-delay product (EDP). Different optimization techniques exist for addressing the problem of mismatch between the dynamic requirement and runtime allocation of the system resources. Choosing between multiple optimizations at runtime is complex due to the non-additive effects, making the scenario suitable for the application of machine learning techniques. We present a novel method, Machine Learned Machines (MLM), by using online reinforcement learning (RL) to perform dynamic partitioning of the last level cache (LLC), along with dynamic voltage and frequency scaling (DVFS) of the core and uncore (interconnection network and LLC). We have proposed and evaluated three different MLM co-optimization techniques based on independent and cooperative multi-agent learners. We show that the co-optimization results in a much lower system EDP than any of the techniques applied individually. We explore various RL models targeted toward optimization of different system metrics and study their effects on a system EDP, system throughput (STP), and Fairness. The various proposed techniques have been extensively evaluated with a mix of 20 workloads on a 4-core system using Spec2006 benchmarks. We have further evaluated our cooperative MLM techniques on a 16-core system. The results show an average of 20.5% and 19.1% system EDP improvement on a 4-core and 16-core system, respectively, with limited degradation of STP and Fairness.
Rahul Jain 0004, Preeti Ranjan Panda, Sreenivas Subramoney
ACM Trans. Archit. Code Optim.1
2016 Machine Learned Machines: Adaptive co-optimization of caches, cores, and On-chip Network
Rahul Jain 0004, Preeti Ranjan Panda, Sreenivas Subramoney
DATE1
2007 An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform
abstract
The discrete wavelet transform (DWT) forms the core of the JPEG2000 image compression algorithm. JPEG2000 standard defines an irreversible DWT by a lifting scheme of factorized coefficients using (9, 7) Daubechies coefficients. The paper proposed optimizations on lifting based 1D-DWT data flow graph resulting in a new pipelining scheme, which is more power-efficient than existing approaches. The authors have shown that the constant multipliers defined by JPEG2000 standard, have latency of about 1.6 times the general adder latency. Hence, while finding the critical path, the basic assumption of multiplier latency being much greater than the adder latency does not hold for DWT in JPEG2000. How 75% multiplications can be reduced at the scaling step by this 2D-DWT implementation was also shown. This multiplication reduction not only saves power but also results in area saving by eliminating three multipliers in the hardware
Rahul Jain 0004, Preeti Ranjan Panda
ISCAS1