In order to reduce the memory access time for a Single-Instruction Multiple-Data stream (SIMD) computer with pq processing elements attached to a host computer, a multiaccess memory system is proposed. The proposed memory system supports simultaneous access to pq data elements within a 4-directional block (p /spl times/ q), a row (1 /spl times/ pq), a column (pq /spl times/ 1), a forward-diagonal, and a backward-diagonal subarray with a constant interval in an arbitrary position in an M /spl times/ N array of data elements, where the number of memory modules, m, is a prime number greater than pq. For the simple and fast address calculation and routing circuit, the address differences between the pq addresses and the base address are arranged in ascending order according to the index numbers of m memory modules from the index number of memory module of the first element. The proposed multiaccess memory system provides more subarray types and more constant intervals than the previous memory systems.

Many current graphical display systems utilize a buffer memory system to contain a two-dimensional image array to be modified and displayed. In order to speed up the update of the buffer memory system, it is required that the buffer memory system accesses many image points within an image subarray in parallel. This paper proposes an efficient buffer memory system for a fast and high-resolution graphical display system. The memory system provides parallel accesses to pq image points within a block(p/spl times/q), a horizontal (1/spl times/pq), a vertical (pq/spl times/1), a forward-diagonal, or a backward-diagonal subarray in a two-dimensional image array, M/spl times/N, where the design parameters p and q are all powers of two. In the address calculation and routing circuit of the proposed buffer memory system, the address differences of the five subarrays are prearranged according to the index numbers of memory modules and stored in two static random access memories (SRAMs), so that the address differences are simply added to the base address to obtain the addresses according to the index numbers of memory modules. In addition, for the fast address calculation, one single multiplication operation in the base address calculation is replaced by a SRAM access, so that the multiplication operation can be performed during the SRAM access for the address differences for the case when N is not a power of two. The address calculation and routing circuit proposed in this paper is improved in the hardware cost, the complexity of control, and the speed over the previous circuits.

In this paper, a memory system is introduced for the efficient construction of a Gaussian pyramid. The memory system consists of an address calculating circuit, an address routing circuit, a memory module selection circuit, and 2/sup n/+1 memory modules. The memory system provides parallel access to 2/sup n/ image points whose patterns are a block, a row or a column, where the interval of the column and the block is 1 and the interval of the row is 2/sup l/,l/spl ges/0. The performance of a generic SIMD (single-instruction multiple-data) processor using the proposed memory system is compared with one using an interleaved memory system for the construction of a Gaussian pyramid. The ratio of the time of the construction of level 2 and level 10 from the original image (level 0) of an SIMD processor with an interleaved memory system to that of the proposed memory system is 1.485 and 1.633, respectively.

Image processing operations require that an image or partial image be stored in a memory system that permits access to p × q, 1 × pq, and/or pq × 1 subarrays of an image array where p and q are design parameters.