Tsunehisa Doi

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4ranked-venue papers

0as first author

0since 2021 · last 1995

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Artificial intelligence and machine learning · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Processor architecture and microarchitecture · 44% Parallel and multicore computing · 44% Interconnection networks and networks-on-chip · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Parallel and multicore computing › multiprocessor system distributed memory parallel computers	1	1994	AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler · ASPLOS 1994
Processor architecture and microarchitecture instruction set architecture	1	1994	AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler · ASPLOS 1994
Interconnection networks and networks-on-chip › interprocessor communication message-passing network	1	1994	AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler · ASPLOS 1994

Methods — techniques the papers use, named apart from their topics

simulation · 0.0

Year	Publication	Venue	Position
1995	HPF Compiler for the AP1000 abstract Article Free Access Share on HPF compiler for the AP1000 Authors: Tatsuya Shindo Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, Japan Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, JapanView Profile , Hidetoshi Iwashita Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, Japan Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, JapanView Profile , Tsunehisa Doi Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, Japan Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, JapanView Profile , Junichi Hagiwara Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, Japan Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, JapanView Profile , Shaun Kaneshiro Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, Japan Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, JapanView Profile Authors Info & Claims ICS '95: Proceedings of the 9th international conference on SupercomputingJuly 1995 Pages 190–194https://doi.org/10.1145/224538.224560Published:03 July 1995Publication History 4citation139DownloadsMetricsTotal Citations4Total Downloads139Last 12 Months5Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF Tatsuya Shindo, Hidetoshi Iwashita, Tsunehisa Doi, Junichi Hagiwara, Shaun Kaneshiro	International Conference on Supercomputing	3
1994	AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler abstract The scalability of distributed-memory parallel computers makes them attractive candidates for solving large-scale problems. New languages, such as HPF, FortranD, and VPP Fortran, have been developed to enable existing software to be easily ported to such machines. Many distributed-memory parallel computers have been built, but none of them support the mechanisms required by such languages. We studied the mechanisms required by parallelizing compilers and proposed a new architecture to support them. Based on this proposed architecture, we developed a new distributed-memory parallel computer, the AP1000+, which is an enhanced version of the AP1000. Using scientific applications in VPP Fortran and C, such as NAS parallel benchmarks, we simulated the performance of the AP1000+. Kenichi Hayashi, Tsunehisa Doi, Takeshi Horie, Yoichi Koyanagi, Osamu Shiraki, Nobutaka Imamura, Toshiyuki Shimizu, Hiroaki Ishihata, Tatsuya Shindo	ASPLOS	2
1994	Twisted data layout abstract This paper proposes twisted data layout as a novel and efficient data layout technique for distributed memory parallel processors (DMPP). Data layout is an important aspect in efficiently executing a parallel program on DMPPs. The optimal data layout pattern for an array may differ throughout the program. Twisted data layout can be used to resolve the conflicts among the optimal array distributions in a special case. Experimental results on the AP1000 multicomputer measure the performance of the twisted data layout scheme. Tatsuya Shindo, Hidetoshi Iwashita, Shaun Kaneshiro, Tsunehisa Doi, Junichi Hagiwara	International Conference on Supercomputing	4
1988	Feedback of correcting information in postediting to a machine translation system Fujio Nishida, Shinobu Takamatsu, Tadaaki Tani, Tsunehisa Doi	COLING	4