For pt. I see ibid., vol. 14, no. 2, p. 218-38 (1995). This part of the paper is focused on a novel application of Qualitative Reasoning, which allows modifications of a circuit's topology to take place in cases where not all performance specifications are met. Within ISAID, this task of post-simulation circuit correction is carried out by the Circuit Corrector.>

The research presented in this paper is concerned with the automation of analog integrated circuit design and, in particular, with a description of methods and techniques employed by the ISAID design system developed at Imperial College, UK. ISAID is comprised of two modules: the circuit generator and the circuit corrector. The circuit generator is based on newly developed methods that are used to handle hierarchical generation of topologies and size MOS transistors so that the performance of designed circuits compare satisfactorily with their specifications. To avoid long design times, simulation is used only after the generation of an initial circuit topology. Simulated performances may therefore be found to differ from the required. One novel feature of the proposed methodology is that in such cases a circuit corrector is invoked to correct the initial design. The circuit corrector is essentially a novel application of qualitative reasoning, which, without iterative simulation analyses performance trade-offs, thereby selects circuit adjustments-transistor size adjustments or topological modifications-that would improve the problematic performances. Several design examples have demonstrated the benefits of the ISAID design approach.>