EDBT 2026 Demo / reviewers in the wild / expert
Chao-Kai Liu
dblp:42/4738
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1978
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorTheory of computation · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
3 papers |
Coding theory · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Integrated circuit design · 58% Distributed systems · 16% Hardware reliability and fault tolerance · 16% |
Topics — the 12 heaviest of 12, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Coding theory
error-correcting codes |
0.0 | 3 | 1978 | Error-Correcting Codes in Binary-Coded-Decimal Arithmetic · IEEE Trans. Computers 1978 On majority-logic-decodable arithmetic codes · IEEE Trans. Inf. Theory 1973 Weight-Preserved Single-Error-Correcting Scheme for Binary Adders · IEEE Trans. Computers 1974 |
Coding theory › error-correcting codes › arithmetic codes
arithmetic error-correcting codes |
0.0 | 2 | 1978 | Error-Correcting Codes in Binary-Coded-Decimal Arithmetic · IEEE Trans. Computers 1978 Weight-Preserved Single-Error-Correcting Scheme for Binary Adders · IEEE Trans. Computers 1974 |
Integrated circuit design › digital circuit design › arithmetic circuit design
adder design |
0.0 | 1 | 1974 | Weight-Preserved Single-Error-Correcting Scheme for Binary Adders · IEEE Trans. Computers 1974 |
Integrated circuit design › digital circuit design
arithmetic circuit design |
0.0 | 1 | 1974 | Weight-Preserved Single-Error-Correcting Scheme for Binary Adders · IEEE Trans. Computers 1974 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1974 | Weight-Preserved Single-Error-Correcting Scheme for Binary Adders · IEEE Trans. Computers 1974 |
Hardware reliability and fault tolerance
error correction |
0.0 | 1 | 1974 | Weight-Preserved Single-Error-Correcting Scheme for Binary Adders · IEEE Trans. Computers 1974 |
Distributed systems
fault tolerance |
0.0 | 1 | 1974 | Weight-Preserved Single-Error-Correcting Scheme for Binary Adders · IEEE Trans. Computers 1974 |
Coding theory › error-correcting codes
arithmetic codes |
0.0 | 1 | 1973 | On majority-logic-decodable arithmetic codes · IEEE Trans. Inf. Theory 1973 |
Coding theory › error-correcting codes
cyclic codes |
0.0 | 1 | 1973 | On majority-logic-decodable arithmetic codes · IEEE Trans. Inf. Theory 1973 |
Coding theory › error-correcting codes › decoding
majority-logic decoding |
0.0 | 1 | 1973 | On majority-logic-decodable arithmetic codes · IEEE Trans. Inf. Theory 1973 |
Processor architecture and microarchitecture
arithmetic unit |
0.0 | 1 | 1978 | Error-Correcting Codes in Binary-Coded-Decimal Arithmetic · IEEE Trans. Computers 1978 |
Integrated circuit design › digital arithmetic circuits › decimal arithmetic
BCD arithmetic |
0.0 | 1 | 1978 | Error-Correcting Codes in Binary-Coded-Decimal Arithmetic · IEEE Trans. Computers 1978 |
Methods — techniques the papers use, named apart from their topics
weight-preserved relation · 0.0number theory · 0.0arithmetic series weight function · 0.0two-step majority-logic decoding · 0.0cyclotomic factor construction · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1978 | Error-Correcting Codes in Binary-Coded-Decimal ArithmeticabstractError-correcting coding schemes devised for binary arithmetic are not in general applicable to BCD arithmetic. In this paper, we investigate the new problem of using such coding schemes in BCD systems. We first discuss the general characteristics of arithmetic errors and define the arithmetic weight and distance in BCD systems. We show that the distance is a metric function. Number theory is used to construct a class of single-error-correcting codes for BCD arithmetic. It is shown that the generator of these codes possesses a very simple form and the structure of these codes can be analytically determined. Chao-Kai Liu, Tse Lin Wang |
IEEE Trans. Computers | 1 |
| 1974 | Weight-Preserved Single-Error-Correcting Scheme for Binary AddersabstractA new single-error-correcting scheme for binary adders is devised in this paper. A new weight function [called the Arithmetic Series Weight Function (ASWF)] of binary integers is defined. By using this weight function, a simple weight-preserved relation among the operands, sums and carries of binary adders is obtained. The error-correcting scheme is based on this relation. The redundancy of this scheme is comparable to that of the other error-control techniques in binary computer arithmetic. Moreover, the error-correcting procedure is simple and can be carried out by solving a simple algebraic equation involving only additive operations. Tse Lin Wang, Chao-Kai Liu |
IEEE Trans. Computers | 2 |
| 1973 | On majority-logic-decodable arithmetic codesabstractA new class of cyclic multiple-error-correcting arithmetic codes is described, and the minimum distance of these codes is determined analytically. A two-step majority-logic decoding scheme is developed for these arithmetic codes. The new class of codes is extended to a new class of arithmetic codes having a primitive cyclotomic factor as the generator and anL-step majority-logic decoding scheme is developed for the extended class of codes. Chin-Long Chen, Robert T. Chien, Chao-Kai Liu |
IEEE Trans. Inf. Theory | 3 |